Semiconductor memory device

Claim 2

A semiconductor memory device comprising a matrix of memory cells, each memory cell comprising: a first MOS transistor (Q1) of a first channel type formed on a semiconductor substrate and having a gate electrode connected to a word line, a drain and a source, the source being connected to a bit line, a charge storage electrode connected to the drain of the first transistor and formed over the gate electrode of the first transistor, being separated from the gate electrode by an insulating film to form a capacitor, a semiconductor layer formed over the charge storage electrode, being separated from the charge storage electrode by an insulating film, a second MOS transistor (Q2) of a second channel type different from the first channel type, formed in the semiconductor layer and having a source and a drain, the charge storage electrode forming a gate electrode of the second MOS transistor, the drain of the second transistor being connected to a power supply, the source of the second transistor being connected to a bit line, which is either the same as or separate from the first-mentioned bit line, said memory device further comprising means for controlling writing and reading of data in and out of the memory cell, said control means writing data by controlling the potential on the word line and the bit line connected to the first MOS transistor to supply an electric charge corresponding to the data on the bit line connected to the first MOS transistor, said control means reading data by controlling the potential on the word line to cause conduction or nonconduction of the second MOS transistor depending on the electric charge stored on the charge storage electrode, thereby providing an output on the bit line connected to the second MOS transistor, the output differing depending on the conduction or nonconduction of the second MOS transistor.

Claim 3

A device according to claim 1, wherein the semiconductor is silicon.

Claim 4

A device according to claim 2, wherein the semiconductor layer is a polysilicon layer.

Claim 5

A device according to claim 1, wherein a diode is formed between the sources of the first and the second MOS transistors.

Claim 6

A device according to claim 1, wherein the source of the first MOS transistor is connected to a bit line for writing, and the source of the second MOS transistor is connected to a bit line for reading, said bit line for reading being separate from the bit line for writing.

Claim 7

A device according to claim 5, wherein a pn junction diode or a Schottky diode is formed between the drain of the second MOS transistor and the charge storage electrode.

Claim 8

A device according to claim 6. wherein the charge storage electrode is of the conductivity type different from the conductivity type of the drain of the first MOS transitor, to form a pn juntion diode between them.

Claim 9

A device according to claim 6, wherein the charge storage electrode is of a metal to form a Schottky junction diode between it and the drain of the first MOS transistor.

Claim 10

A semiconductor memory device comprising a memory cell, which comprises a first MOS transistor (Q1) of a first channel type formed on a semiconductor substrate and having a gate electrode connected to a word line, a drain and a source, the source being connected to a bit line, a charge storage electrode connected to the drain of the first transistor and formed over the gate electrode of the first transistor, being separated from the gate electrode by an insulating film to form a capacitor, a semiconductor layer formed over the charge storage electrode, being separated from the charge storage electrode by an insulating film, a second MOS transistor (Q2) of a second channel type different from the first channel type, formed in the semiconductor layer and having a source and a drain, the charge storage electrode forming a gate electrode of the second MOS transistor, the drain of the second transistor being connected to a power supply, the source of the second transistor being connected to a bit line, which is either the same as or separate from the first-mentioned bit line, said memory device further comprising means for controlling writing and reading of data in and out of the memory cell, said control means applying a first potential to the word line to make conductive the first MOS transistor for writing data, applying a first potential to the source of the first MOS transistor, for writing data "1", and applying a second potential to the source of the first MOS transistor for writing data "0", said control means applying a second potential to the word line to keep the first transistor nonconductive for maintaining the data stored on the charge storage electrode, said control means applying a third potential to the word line for reading data, to change the potential on the charge storage electrode to make the second MOS transistor conductive or nonconductive depending on the data stored on the charge storage electrode, thereby transmitting or not transmitting the potential from the power supply to the source of the second MOS transistor and hence to the bit line connected thereto, the transmission and nontransmission of the potential from the power supply providing different potentials on the bit line connected to the source of the second transistor.

Claim 11

A semiconductor memory device comprising a memory cell, which comprises a first MOS transistor (Q1) of a first channel type formed on a semiconductor substrate and having a gate electrode connected to a word line, a drain and a source, the source being connected to a bit line, a charge storage electrode connected to the drain of the first transistor and formed over the gate electrode of the first transistor, being separated from the gate electrode by an insulating film to form a capacitor, a semiconductor layer formed over the charge storage electrode, being separated from the charge storage electrode by an insulating film, a second MOS transistor (Q2) of a second channel type different from the first channel type, formed in the semiconductor layer and having a source and a drain, the charge storage electrode forming a gate electrode of the second MOS transistor, the drain of the second transistor being connected to a power supply, the source of the second transistor being connected to a bit line, which is either the same as or separate from the first-mentioned bit line, said memory device further comprising means for controlling writing and reading of data in and out of the memory cell, said control means applying a first potential to the word line to make conductive the first MOS transistor for writing data, applying a first potential to the source of the first MOS transistor, for writing data "1", and applying a second potential to the source of the first MOS transistor for writing data "0", said control means applying a second potential to the word line to keep the first transistor nonconductive for maintaining the data stored on the charge storage electrode, said control means applying a third potential to the word line for reading data, to change the potential on the charge storage electrode to make the second MOS transistor conductive or nonconductive depending on the data stored on the charge storage electrode, thereby transmitting or not transmitting the potential from the power supply to the source of the second MOS transistor and hence to the bit line connected thereto, the transmission and nontransmission of the potential from the power supply providing different potentials on the bit line connected to the source of the second transistor.

Claim 12

A device according to claim 9, wherein the semiconductor is silicon.

Claim 13

A device according to claim 10, wherein the first MOS transistor is an n-channel transistor, and the second MOS transistor is a p-channel transistor, and the third potential as applied to the word line is lower than the second potential as applied to the word line, which in turn is lower than the first potential as applied to the word line, and the second potential as applied to the source of the first MOS transistor is lower than the first potential as applied to the source of the second MOS transistor.

Claim 14

A device according to claim 10, wherein the semiconductor layer is a polysilicon layer.

Claim 15

A device according to claim 9, wherein a diode is formed between the sources of the first and the second MOS transistors.

Claim 16

A device according to claim 13, wherein the source of the first MOS transistor and the source of the second MOS transistor are in contact with each other to form a pn junction diode, and the source of the second transistor is connected to the common bit line used both for writing and reading.

Claim 17

A device according to claim 13, wherein the source of the first MOS transistor and the source of the second MOS transistor are in contact with each other through a metal layer to form a pn Schottky junction diode between the metal layer and the one of the sources, and the source of the second transistor is connected to a common bit line used both for writing and reading.

Claim 18

A device according to claim 9, wherein the source of the first MOS transistor is connected to a bit line for writing, and the source of the second MOS transistor is connected to a bit line for reading, said bit line for reading being separate from the bit line for writing.

Claim 19

A device according to claim 16, wherein a pn junction diode or a Schottky diode is formed between the drain of the second MOS transistor and the charge storage electrode.

Claim 20

A device according to claim 17, wherein the charge storage electrode is of the conductivity type different from the conductivity type of the drain of the first MOS transistor, to form a pn junction diode between them.

Claim 21

A device according to claim 17, wherein the charge storage electrode is of a metal to form a Schottky junction diode between it and the drain of the first MOS transistor.

Claim 22

A device according to claim 9, wherein the channels of the first and the second transistors extend in a direction of the bit lines and the word lines extend in a direction orthogonal to the direction of the bit lines.