Read only memory device

Claim 2

A read only semiconductor memory device comprising: a plurality of transistor pairs arranged in a matrix manner; each transistor pair comprising a transistor of one conductivity type responsive to one input to output a high level logic, and a transistor of an opposite conductivity type responsive to one input to output a low level logic; input lines for connecting transistors of the same columns of said transistor pairs; and output lines for connecting transistors of the same rows of said transistor pairs, thus allowing only one of two transistors constituting said transistor pair to be operated thereby to obtain a predetermined logical output; said transistor of said one conductivity type being operated so as to raise a potential on said output line to high level, said transistor of the other conductivity type being operated so as to pull down a potential on said output line to low level; said matrix being configurated as a CMOS master chip on which two conductivity type transistors are regularly arranged.

Claim 3

A read only semiconductor memory device comprising: a plurality of transistor pairs arranged in a matrix manner, each transistor pair comprising two transistors of one conductivity type and the other conductivity type which are commonly connected at their sources and drains, respectively, input lines for connecting transistors of the same columns of said transistor pairs, and output line for connecting transistors of the same rows of said transistor pairs, a common connecting point for sources of the transistor pair for outputting one logic being connected to a source for delivering one level, and a common connecting point for sources of the transistor pair for outputting the other logic being connected to a source for delivering the other level, said matrix being configurated as a CMOS master chip on which the two conductivity type transistors are regularly arranged.

Claim 4

A read only semiconductor memory device comprising: a plurality of transistor pairs arranged in a matrix manner, each transistor pair comprising two transistors of one conductivity type and the other conductivity type which are commonly connected at their sources and drains, respectively, input lines for connecting transistors of the same columns of said transistor pairs, and output line for connecting transistors of the same rows of said transistor pairs, a common connecting point for sources of the transistor pair for outputting one logic being connected to a source for delivering one level, and a common connecting point for sources of the transistor pair for outputting the other logic being connected to a source for delivering the other level, said matrix being configurated as a CMOS master chip on which the two conductivity type transistors are regularly arranged.

Claim 5

A read only semiconductor memory device comprising: a plurality of transistor pairs arranged in a matrix manner, each transistor pair comprising a transistor of one conductivity type responsive to one input to output one logic and a transistor of an opposite conductivity type responsive to one input to output the other logic; input lines for connecting transistors of the same columns of said transistor pairs, output lines for connecting transistors of the same rows of said transistor pairs, the transistor pairs which output one logic being commonly connected at their sources and drains, respectively, a common connecting point for sources being connected to a source for said one level, and a common connecting point for drains being connected to said output line; the transistor pairs which output the other logic being such that only the transistors of said opposite conductivity type for pulling down a potential on said output line to the other level is operated; said matrix being configurated as a CMOS master chip on which the two conductivity type transistors are regularly arranged.

Claim 6

A read only semiconductor memory device comprising: a plurality of transistor pairs arranged in a matrix manner, each transistor pair comprising a transistor of one conductivity type responsive to one input to output one logic and a transistor of an opposite conductivity type responsive to one input to output the other logic; input lines for connecting transistors of the same columns of said transistor pairs, output lines for connecting transistors of the same rows of said transistor pairs, the transistor pairs which output one logic being commonly connected at their sources and drains, respectively, a common connecting point for sources being connected to a source for said one level, and a common connecting point for drains being connected to said output line; the transistor pairs which output the other logic being such that only the transistors of said opposite conductivity type for pulling down a potential on said output line to the other level is operated; said matrix being configurated as a CMOS master chip on which the two conductivity type transistors are regularly arranged.

Claim 7

The read only semiconductor memory device as set forth in claim 1, wherein said transistor of said one conductivity type is a p-channel transistor, and said transistor of said opposite conductivity type is an n-channel transistor.

Claim 8

The read only semiconductor memory device as set forth in claim 1, wherein each of said input lines is a word line, and each of said output lines is a bit line.

Claim 9

The read only semiconductor memory device as set forth in claim 4, wherein said p-channel transistor for outputting high level logic has a source connected to a drain supply voltage V DD , a gate connected to said word line, and a drain connected to said bit line, and said n-channel transistor for outputting low level logic has a source connected to a source supply voltage V SS , a gate connected to a word line of an opposite logic to said word line, and a drain connected to said bit line.

Claim 10

The read only semiconductor memory device as set forth in claim 6, wherein the transistor which does not produce a logic output of said transistor pairs has a connection relationship such that at least one of its source and drain is not connected.

Claim 11

The read only semiconductor memory device as set forth in claim 7, wherein the gate of said transistor which does not produce a logical output is not connected to said word line.

Claim 12

The read only semiconductor memory device as set forth in claim 1, wherein each of said transistor pairs is representative of a unit logical output of a gate array.

Claim 13

The read only semiconductor memory device as set forth in claim 1, wherein each of said transistor pairs is representative of a unit logical output of a read only semiconductor memory unit.

Claim 14

The read only semiconductor memory device as set forth in claim 2, wherein said one level and the other level represent a drain supply voltage V DD and a source supply voltage V SS , respectively, said one logic and the other logic represent high level logic and low level logic, respectively, and said transistors of said one conductivity type and opposite conductivity type represent a p-channel transistor and an n-channel transistor, respectively.

Claim 15

The read only semiconductor memory device as set forth in claim 11, wherein said input lines are word lines logically opposite to each other commonly connected to the gate of the transistor of said one conductivity type of the transistors of the same column, and each of said output lines is a bit line connected to the drain common junction of the transistor pairs of the same row.

Claim 16

The read only semiconductor memory device as set forth in claim 3, wherein said one level and the other level represent drain and source power supply voltages, respectively, said one logic and the other logic represent high level logic and low level logic, respectively, said transistor of said one conductivity type being a p-channel transistor, said transistor of said the other conductivity type being an n-channel transistor.

Claim 17

The read only semiconductor memory device as set forth in claim 13, wherein said input line is word lines logically opposite to each other commonly connected to gates of transistors of the same conductivity type of said transistor pairs, said output line is a bit line connected to a drain common junction of the transistor pairs of the same row.