US4779228A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Sequential-access memory
Assignee: Yamaha Corp
•
Filing: 1986-12-23
•
Granted: 1988-10-18
•
Expires: 2006-12-23
Abstract
Abstract A sequential-access memory of an auto-refreshing type has an increased storage capacity. The sequential-access memory has at least two dynamic-type memory cell arrays serially connected to one another to form a loop. Each array comprises N rows by M columns of memory cells each having a read selection line and a write selection line. The read selection line of each memory cell of each row is connected to the write selection line of the memory cell of the same row which comes next to the each memory cell to form an address selection line. The address selection lines of each memory cell array are activated one after another to effect a sequential access to the memory cell array. Data read form each memory cell array is fed through a delay circuit to the memory cell array which comes next to the each memory cell array. A logic circuit for subjecting data outputted from one memory array may be additionally provided to feed data representative of the result of the predetermined operation to the next memory array.
Inventors
- 👤 Yasuji Uchiyama
- 👤 Shigeki Yamamoto
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 21:36
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C11/409; G11C11/408; G11C8/00; G11C8/04
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
261 words
A sequential-access memory comprising: (a) a plurality of memory cell arrays arranged so that at least two memory cell arrays are adjoining, each memory cell array comprising a plurality of dynamic-type memory cells each having a write selection line, a read selection line, a data output line and a data input line, said plurality of memory cells being arranged to form at least one row of memory cells in such a manner that the read selection line of each memory cell is connected to the write selection line of the memory cell which comes next to said each memory cell to form an address selection line, the data output lines of said plurality of memory cells being connected together to form a read data line, said data input lines of said plurality of memory cells being connected together to form a write data line; (b) access control means for activating the address selection lines of each of said memory cell arrays one after another at a predetermined time interval; and (c) delay circuit means interposed between each adjoining pair of memory cell arrays among said memory cell arrays to connect said memory arrays in series in such a manner than data on said read data line of each memory cell array is delayed by a predetermined time interval and fed to said write data line of the memory cell array which comes next to said each memory cell array, the data on said read data line not being fed from said delay circuit means back to said each memory cell array.
Claim 2
Dependent Claim
261 words
A sequential-access memory comprising: (a) a plurality of memory cell arrays arranged so that at least two memory cell arrays are adjoining, each memory cell array comprising a plurality of dynamic-type memory cells each having a write selection line, a read selection line, a data output line and a data input line, said plurality of memory cells being arranged to form at least one row of memory cells in such a manner that the read selection line of each memory cell is connected to the write selection line of the memory cell which comes next to said each memory cell to form an address selection line, the data output lines of said plurality of memory cells being connected together to form a read data line, said data input lines of said plurality of memory cells being connected together to form a write data line; (b) access control means for activating the address selection lines of each of said memory cell arrays one after another at a predetermined time interval; and (c) delay circuit means interposed between each adjoining pair of memory cell arrays among said memory cell arrays to connect said memory arrays in series in such a manner than data on said read data line of each memory cell array is delayed by a predetermined time interval and fed to said write data line of the memory cell array which comes next to said each memory cell array, the data on said read data line not being fed from said delay circuit means back to said each memory cell array.
Claim 3
Dependent Claim
339 words
A sequential-access memory comprising: (a) a plurality of memory cell arrays arranged so that at least two memory cell arrays are adjoining, each memory cell array comprising a plurality of dynamic-type memory cells each having a write selection line, a read selection line, a data output line and a data input line, said plurality of memory cells being arranged to form at least one row of memory cells in such a manner that the read selection line of each memory cell is connected to the write selection line of the memory cell which comes next to said each memory cell to form an address selection line, the data output lines of said plurality of memory cells being connected together to form a read data line, said data input ines of said plurality of memory cells being connected together to form a write data line; (b) access control means for activating the address selection lines of each of said memory cell arrays one after another at a predetermined time interval; and (c) delay circuit means interposed between each adjoining pair of memory cell arrays among said memory cell arrays to connect said memory arrays in series in such a manner than data on said read data line of each memory cell array is delayed by a predetermined time interval and fed to said write data line of the memory cell array which comes next to said each memory cell array; each of said memory cell arrays further comprising least one additional row of memory cells each identical in structure to said at least one row of memory cells, said address selection lines of said at least one row of memory cells being connected respectively to the corresponding address selection lines of said additional row of memory cells, said delay circuit means delaying data fed from said read data lines of each memory cell array by said predetermined time interval and feeding to said write data ines of the memory cell array which comes next to said each memory cell array.
Claim 4
Dependent Claim
339 words
A sequential-access memory comprising: (a) a plurality of memory cell arrays arranged so that at least two memory cell arrays are adjoining, each memory cell array comprising a plurality of dynamic-type memory cells each having a write selection line, a read selection line, a data output line and a data input line, said plurality of memory cells being arranged to form at least one row of memory cells in such a manner that the read selection line of each memory cell is connected to the write selection line of the memory cell which comes next to said each memory cell to form an address selection line, the data output lines of said plurality of memory cells being connected together to form a read data line, said data input ines of said plurality of memory cells being connected together to form a write data line; (b) access control means for activating the address selection lines of each of said memory cell arrays one after another at a predetermined time interval; and (c) delay circuit means interposed between each adjoining pair of memory cell arrays among said memory cell arrays to connect said memory arrays in series in such a manner than data on said read data line of each memory cell array is delayed by a predetermined time interval and fed to said write data line of the memory cell array which comes next to said each memory cell array; each of said memory cell arrays further comprising least one additional row of memory cells each identical in structure to said at least one row of memory cells, said address selection lines of said at least one row of memory cells being connected respectively to the corresponding address selection lines of said additional row of memory cells, said delay circuit means delaying data fed from said read data lines of each memory cell array by said predetermined time interval and feeding to said write data ines of the memory cell array which comes next to said each memory cell array.
Claim 5
Dependent Claim
91 words
A sequential-access memory according to claim 2, wherein one of said delay circuit means comprises a logic circuit for subjecting data inputted from the read data lines of the memory cell array connected to input side of said one delay circuit means to a predetermined operation and for outputting data representative of the result of said predetermine operation to the write data lines of the memory cell array connected to output side of said one delay circuit means in a delayed relation by a predetermined time period to said inputted data.
Claim 6
Dependent Claim
30 words
A sequential-access memory according to claim 3, wherein said predetermined operation effected by said logic circuit is an addition of said inputted data to data fed from an external circuit.
References Cited (Backward Citations)
US3555521A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-10-18 | 1992-04-18 | 1992-10-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-10-18 | 1996-04-18 | 1996-10-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-10-18 | 2000-04-18 | 2000-10-18 | $7700.00 | Window Closed / Lapsed |