Power semiconductor device with main current section and emulation current section

Claim 2

A power semiconductor device comprising: an active region having a perimeter and including a plurality of active region cells, a first subset of said cells constituting a main current section and a second subset of said cells constituting an emulation current section, each of said subsets including more than one of said cells; a common anode contacting said main current section and said emulation current section; a first cathode contacting each of said cells of said first subset and none of said cells of said second subset; a second cathode separate from said first cathode contacting each of said cells of said second subset and none of said cells of said first subset; a common device termination region surrounding said active region; and said cells of said second subset being distributed at various distances from said perimeter, with a larger number of said second cells being disposed at relatively small distances from said perimeter than are disposed at relatively large distances from said perimeter whereby the current level in said emulation current section is closely proportional to the current level in said main current section during device turn-on and turn-off.

Claim 3

The power semiconductor device of claim 1 further including a second gate coupled to said emulation current section.

Claim 4

The power semiconductor device of claim 2 wherein said first and second gates comprise a commonly-interconnected gate.

Claim 5

A power semiconductor device comprising: an active region including a plurality of active region cells which are substantially identical in size and structure to each other, at least three of said cells constituting an emulation current section and others of said cells constituting a main current section, said main current section comprising more cells than said emulation current section; a common power contact contacting said main current section and said emulation current section; a first power contact contacting said main current section and not contacting said emulation current section; a second power contact spaced from said first power contact contacting said emulation current section and not contacting said main current section; a common device termination region surrounding said active region including said main current section and said emulation current section; and said cells of said emulation current section being distributed at various distances from said perimeter, with a larger number of said emulation current cells being disposed at relatively small distances from said perimeter than at relatively large distances from said perimeter, whereby the current level in said emulation current section is closely proportional to the current level in said main current section during device turn-on and turn-off.

Claim 6

A power semiconductor device comprising: an active region including a plurality of active region cells which are substantially identical in size and structure to each other, at least three of said cells constituting an emulation current section and others of said cells constituting a main current section, said main current section comprising more cells than said emulation current section; a common power contact contacting said main current section and said emulation current section; a first power contact contacting said main current section and not contacting said emulation current section; a second power contact spaced from said first power contact contacting said emulation current section and not contacting said main current section; a common device termination region surrounding said active region including said main current section and said emulation current section; and said cells of said emulation current section being distributed at various distances from said perimeter, with a larger number of said emulation current cells being disposed at relatively small distances from said perimeter than at relatively large distances from said perimeter, whereby the current level in said emulation current section is closely proportional to the current level in said main current section during device turn-on and turn-off.

Claim 7

The semiconductor device of claim 1 wherein said active region cells each comprise insulated gate transistor cells.

Claim 8

The power semiconductor device of claim 1 wherein said active region comprises silicon semiconductor material.

Claim 9

The power semiconductor device of claim 1 further including a first gate coupled to said main current section.

Claim 10

The semiconductor power device recited in claim 1 wherein said emulation current section is generally wedge shaped and is disposed with the narrow end of the wedge near the center of said active region and the wide end of the wedge near said perimeter of said active region.

Claim 11

A power semiconductor device comprising: an active region having a perimeter including a main current section incIuding a first plurality of main current cells and an emulation current section including a second plurality of emulation current cells; a common first power contact contacting said main current cells and said emulation current cells; a second contact contacting said main current cells and not contacting said emulation current cells; a third power contact spaced from said second power contact and contacting said emulation current cells and not contacting said main current cells; a common device termination region surrounding said active region; and said emulation current cells being distributed within said active region in a manner in which a larger number of said emulation current cells are disposed relatiely close to said perimeter than are disposed relatively far from said perimeter, which causes the current in said emulation current section to have a known relationship to the current in the main current section during turn-on and turn-off.

Claim 12

A power semiconductor device comprising: an active region having a perimeter including a main current section incIuding a first plurality of main current cells and an emulation current section including a second plurality of emulation current cells; a common first power contact contacting said main current cells and said emulation current cells; a second contact contacting said main current cells and not contacting said emulation current cells; a third power contact spaced from said second power contact and contacting said emulation current cells and not contacting said main current cells; a common device termination region surrounding said active region; and said emulation current cells being distributed within said active region in a manner in which a larger number of said emulation current cells are disposed relatiely close to said perimeter than are disposed relatively far from said perimeter, which causes the current in said emulation current section to have a known relationship to the current in the main current section during turn-on and turn-off.

Claim 13

The power semiconductor device recited in claim 9 wherein the current in said emulation current section is a constant times the current in said main current section.

Claim 14

The power semiconductor device recited in claim 9 wherein the structure of each of said current emulation cells is substantially identical to the structure of a main current cell.

Claim 15

The power semiconductor device recited in claim 11 wherein the current in an emulation current cell is a constant times the current in a main current cell.

Claim 16

The power semiconductor device recited in claim 9 wherein: some of said main current cells are disposed adjacent said perimeter.

Claim 17

The power semiconductor device recited in claim 9 wherein: a majority of said active region cells which are disposed adjacent said perimeter are main current cells.

Claim 18

The power semiconductor device recited in claim 1 wherein: some of said main current cells are disposed adjacent said perimeter.

Claim 19

The power semiconductor device recited in claim 1 wherein: a majority of said active region cells which are disposed adjacent said perimeter are main current cells.

Claim 20

The power semiconductor device recited in claim 4 wherein: some of said main current cells are disposed adjacent said perimeter.

Claim 21

The power semiconductor device recited in claim 4 wherein: a majority of said active region cells which are disposed adjacent said perimeter are main current cells.