US4785201A
Expired / Lapsed
US
⏱️ 0.0 years remaining
High speed/high drive CMOS output buffer with inductive bounce suppression
Assignee: Renesas Electronics America Inc
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Filing: 1986-12-29
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Granted: 1988-11-15
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Expires: 2006-12-29
Abstract
Abstract An output buffer is disclosed which employs a first pair of transistors connected in an (N-channel over P-channel) totem pole configuration, a second pair of transistors connected in a (P-channel over N-channel) totem pole configuration in parallel with the first pair of transistors, and a pair of inverters connected to delay the drive to the second pair of transistors.
Inventors
- 👤 Marcelo A. Martinez
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 16:13
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/003; H03K19/00346; H03K19/00361
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
156 words
An output buffer comprising in combination: a line for connection to receive an externally developed power supply potential; a line upon which the output buffer develops a data output signal; coupling means for coupling said power supply potential line to said data output signal line; a line for connection to receive an externally developed circuit ground potential; a line for connection to receive an externally developed first data input signal; first delay means including a data input connected to said first data input signal line and a data output; an N-channel transistor including a gate connected to said first delay means data output, drain means connected to said data output signal line, and source means connected to said circuit ground potential line; and a P-channel transistor including a gate connected to said first delay means data input, source means connected to said data output signal line, and drain means connected to said circuit ground potential line.
Claim 2
Dependent Claim
156 words
An output buffer comprising in combination: a line for connection to receive an externally developed power supply potential; a line upon which the output buffer develops a data output signal; coupling means for coupling said power supply potential line to said data output signal line; a line for connection to receive an externally developed circuit ground potential; a line for connection to receive an externally developed first data input signal; first delay means including a data input connected to said first data input signal line and a data output; an N-channel transistor including a gate connected to said first delay means data output, drain means connected to said data output signal line, and source means connected to said circuit ground potential line; and a P-channel transistor including a gate connected to said first delay means data input, source means connected to said data output signal line, and drain means connected to said circuit ground potential line.
Claim 3
Dependent Claim
22 words
An output buffer as recited in claim 1 wherein said first transistor has a channel length which is less than two microns.
Claim 4
Dependent Claim
24 words
An output buffer as recited in claim 1 wherein said first delay means includes a pair of transistors connected in a totem pole configuration.
Claim 5
Dependent Claim
60 words
An output buffer as recited in claim 1 wherein said coupling means includes a line for connection to receive an externally developed second data input signal and a third transistor having a gate connected to said second data input signal line, drain means connected to said power supply potential line, and source means connected to said data output signal line.
Claim 6
Dependent Claim
67 words
An output buffer as recited in claim 4 wherein said coupling means further includes second delay means including a data input connected to said second data input signal line and a data output and a fourth transistor having a gate connected to said second delay means data output, source means connected to said power supply potential line, and drain means connected to said data output signal line.
Claim 7
Dependent Claim
25 words
An output buffer as recited in claim 5 wherein said third transistor is an N-channel transistor and wherein said fourth transistor is a P-channel transistor.
Claim 8
Dependent Claim
24 words
An output buffer as recited in claim 5 wherein said second delay means includes a pair of transistors connected in a totem pole configuration.
Claim 9
Dependent Claim
26 words
An output buffer as recited in claim 5 wherein said power supply potential line and said circuit ground potential line are shared with another output buffer.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-11-15 | 1992-05-16 | 1992-11-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-11-15 | 1996-05-16 | 1996-11-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-11-15 | 2000-05-16 | 2000-11-15 | $7700.00 | Window Closed / Lapsed |