US4785410A
Expired / Lapsed
US
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Maximum length shift register sequences generator
Assignee: Faurecia Clarion Electronics Co Ltd
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Filing: 1986-06-02
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Granted: 1988-11-15
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Expires: 2006-06-02
Abstract
Abstract A maximum length shift register sequence generator capable of changing the format and phase of an M code known as maximum length shift register sequences in the transmitter and receiver. The register is most suitable for use in spread spectrum communication systems adapted to effect transmission by correlation between an M code from the transmitter and such an M code generated in the receiver. The generator includes a latch for storing the format and initial phase of an M code to be generated subsequently, and a microprocessor for setting in the latch necessary data required for changing the M code. A change of the M code is effected by a strobe signal lasting for a time equal to the lasting time of one clock pulse.
Inventors
- 👤 Masahiro Hamatsu
- 👤 Takao Kurihara
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 06:04
CPC Classifications
H; H04; H04J; H04J13/00; H04J13/0007; H04J13/0022; H04J13/0025; H03; H03K; H03K3/00; H03K3/84; H04J13/10; H04L; H04L9/00; H04L9/06; H04L9/065; H04L9/0656; H04L9/0662
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
382 words
A maximum length shift register sequences generator, comprising; a plurality of flip-flops which each have a clock input, a data input and a data output; a plurality of switching gates which each have first and second data inputs and a data output, said data output of each said switching gate being coupled to the data input of a respective one of said flip-flops; means for applying a clock pulse to said clock input of each of said flip-flops; a multiplexer having a plurality of data inputs which are each coupled to the data output of a respective one of said flip-flops, having a data output, and having select inputs which specify which one of said data inputs thereof is to be coupled by said multiplexer to said data output thereof; a plurality of AND gates which each have first and second input terminals, said first input terminal of each said AND gate being coupled to said data output of said multiplexer, and said AND gates each having an output; a plurality of feedback circuits which each have one input coupled to the output of a respective one of said AND gates, have a further input coupled to the data output of a respective one of said flip-flops, and have an output, one of said switching gates having its first data input coupled to said data output of said multiplexer and each of the others of said switching gates having its first input coupled to the output of a respective one of said feedback circuits; a first latch having a plurality of outputs which are each coupled to the second data input of a respective one of said switching gates; a second latch having a plurality of outputs which are each coupled to the second input terminal of a respective one of said AND gates; means for applying to each of said switching gates a gate control signal which selects a respective one of said first and second data inputs to be coupled by the switching gate to its data output; a third latch controlled by said gate control signal and having outputs coupled to said select inputs of said multiplexer; and a microprocessor responsive to said gate control signal to supply each of said first, second and third latches with instruction words.
Claim 2
Dependent Claim
382 words
A maximum length shift register sequences generator, comprising; a plurality of flip-flops which each have a clock input, a data input and a data output; a plurality of switching gates which each have first and second data inputs and a data output, said data output of each said switching gate being coupled to the data input of a respective one of said flip-flops; means for applying a clock pulse to said clock input of each of said flip-flops; a multiplexer having a plurality of data inputs which are each coupled to the data output of a respective one of said flip-flops, having a data output, and having select inputs which specify which one of said data inputs thereof is to be coupled by said multiplexer to said data output thereof; a plurality of AND gates which each have first and second input terminals, said first input terminal of each said AND gate being coupled to said data output of said multiplexer, and said AND gates each having an output; a plurality of feedback circuits which each have one input coupled to the output of a respective one of said AND gates, have a further input coupled to the data output of a respective one of said flip-flops, and have an output, one of said switching gates having its first data input coupled to said data output of said multiplexer and each of the others of said switching gates having its first input coupled to the output of a respective one of said feedback circuits; a first latch having a plurality of outputs which are each coupled to the second data input of a respective one of said switching gates; a second latch having a plurality of outputs which are each coupled to the second input terminal of a respective one of said AND gates; means for applying to each of said switching gates a gate control signal which selects a respective one of said first and second data inputs to be coupled by the switching gate to its data output; a third latch controlled by said gate control signal and having outputs coupled to said select inputs of said multiplexer; and a microprocessor responsive to said gate control signal to supply each of said first, second and third latches with instruction words.
Claim 3
Dependent Claim
16 words
A generator according to claim 1, wherein each said feedback circuit is an exclusive OR gate.
Claim 4
Dependent Claim
300 words
A maximum length shift register sequences generator, comprising: a plurality of code generating circuits which each include a flip-flop having a data input, a data output and a clock input, a switching gate having first and second data inputs and having a data output coupled to the data input of the flip-flop, and an AND gate having a first input terminal connected to the data output of the flip-flop, having a second input terminal, and having a data output; means for applying a clock pulse to said clock input of each of said flip-flops; a feedback circuit having a plurality of inputs which are each coupled to the data output of respective one of said AND gates and having an output, the first data input of the switching gate of one said code generating circuit being coupled to said output of said feedback circuit and the first data input of the switching gate of every other said code generating circuit being connected to the data output of the flip-flop of a respective said code generating circuit; a first latch having a plurality of outputs which are each coupled to the second data input of a respective one of said switching gates; a second latch having a plurality of outputs which are each coupled to the second input terminal of a respective one of said AND gates; means for applying to each of said switching gates a gate control signal which selects a respective one of the first and second data inputs thereof to be coupled by the switching gate to its data output; and means responsive to said gate control signal for supplying each of said first and second latches with instruction words; the output of the flip-flop of said one of said code generating circuits producing an M code.
Claim 5
Dependent Claim
300 words
A maximum length shift register sequences generator, comprising: a plurality of code generating circuits which each include a flip-flop having a data input, a data output and a clock input, a switching gate having first and second data inputs and having a data output coupled to the data input of the flip-flop, and an AND gate having a first input terminal connected to the data output of the flip-flop, having a second input terminal, and having a data output; means for applying a clock pulse to said clock input of each of said flip-flops; a feedback circuit having a plurality of inputs which are each coupled to the data output of respective one of said AND gates and having an output, the first data input of the switching gate of one said code generating circuit being coupled to said output of said feedback circuit and the first data input of the switching gate of every other said code generating circuit being connected to the data output of the flip-flop of a respective said code generating circuit; a first latch having a plurality of outputs which are each coupled to the second data input of a respective one of said switching gates; a second latch having a plurality of outputs which are each coupled to the second input terminal of a respective one of said AND gates; means for applying to each of said switching gates a gate control signal which selects a respective one of the first and second data inputs thereof to be coupled by the switching gate to its data output; and means responsive to said gate control signal for supplying each of said first and second latches with instruction words; the output of the flip-flop of said one of said code generating circuits producing an M code.
Claim 6
Dependent Claim
118 words
A generator according to claim 3, wherein said feedback circuit includes a plurality of exclusive OR gates each having a first input connected to the output of a respective one of said AND gates, having a second input, and having an output, a first said exclusive OR gate having its output connected to said first data input of said switching gate of said one code generating circuit, and a second said exclusive OR gate having its second input connected to ground, said second input of each said exclusive OR gate other than said second exclusive OR gate being connected to the output of a respective one of said exclusive OR gates other than said first exclusive OR gate.
Claim 7
Dependent Claim
16 words
A generator according to claim 3, wherein said means for supplying instruction words includes a microprocessor.
Claim 8
Dependent Claim
362 words
A maximum length shift register sequences generator, comprising: a plurality of code generating circuits which each include a flip-flop having a data input, a data output and a clock input, and a switching gate having first and second data inputs and having a data output coupled to the data input of the flip-flop; a plurality of AND gates each having first and second input terminals and having an output terminal; means for applying a clock pulse to said clock input of each of said flip-flops; a multiplexer having a plurality of inputs which are each coupled to the output of a respective one of said flip-flops, having an output which is coupled to said first input terminal of each of said AND gates and to said first input of said switching gate of one of said code generating circuits, and having select inputs which specify which one of said data inputs thereof is to be coupled by said multiplexer to its data output; a first latch having a plurality of outputs which are each coupled to the second data input of a respective one of said switching gates; a second latch having a plurality of outputs which are each coupled to the second input terminal of a respective one of said AND gates; means for applying to each of said switching gates a gate control signal which selects a respective one of the first and second data inputs thereof to be coupled by the switching gate to its data output; a third latch controlled by said gate control signal and having outputs coupled to said select inputs of said multiplexer; a plurality of feedback circuits each having an output coupled to the first data input of the switching gate of a respective said code generating circuit other than said one code generating circuit, having a first input coupled to the output terminal of a respective one of said AND gates, and having a second input coupled to the output of the flip-flop of a respective one of said code generating circuits; and means responsive to said gate control signal for supplying each of said first, second and third latches with instruction words.
Claim 9
Dependent Claim
362 words
A maximum length shift register sequences generator, comprising: a plurality of code generating circuits which each include a flip-flop having a data input, a data output and a clock input, and a switching gate having first and second data inputs and having a data output coupled to the data input of the flip-flop; a plurality of AND gates each having first and second input terminals and having an output terminal; means for applying a clock pulse to said clock input of each of said flip-flops; a multiplexer having a plurality of inputs which are each coupled to the output of a respective one of said flip-flops, having an output which is coupled to said first input terminal of each of said AND gates and to said first input of said switching gate of one of said code generating circuits, and having select inputs which specify which one of said data inputs thereof is to be coupled by said multiplexer to its data output; a first latch having a plurality of outputs which are each coupled to the second data input of a respective one of said switching gates; a second latch having a plurality of outputs which are each coupled to the second input terminal of a respective one of said AND gates; means for applying to each of said switching gates a gate control signal which selects a respective one of the first and second data inputs thereof to be coupled by the switching gate to its data output; a third latch controlled by said gate control signal and having outputs coupled to said select inputs of said multiplexer; a plurality of feedback circuits each having an output coupled to the first data input of the switching gate of a respective said code generating circuit other than said one code generating circuit, having a first input coupled to the output terminal of a respective one of said AND gates, and having a second input coupled to the output of the flip-flop of a respective one of said code generating circuits; and means responsive to said gate control signal for supplying each of said first, second and third latches with instruction words.
Claim 10
Dependent Claim
16 words
A generator according to claim 6, wherein each said feedback circuit is an exclusive OR gate.
Claim 11
Dependent Claim
16 words
A generator according to claim 6, wherein said means for supplying instruction words includes a microprocessor.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-11-15 | 1992-05-16 | 1992-11-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-11-15 | 1996-05-16 | 1996-11-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-11-15 | 2000-05-16 | 2000-11-15 | $7700.00 | Window Closed / Lapsed |