Superconducting switching circuit, memory cell and memory circuit, with resonance damping resistors

Claim 2

A superconducting switching circuit comprising: first and second Josephson junction elements connected in series; first and second excitation inductors connected in series to each other and connected in series to said first and second Josephson junction elements; an exciting line magnetically coupled to said first and second excitation inductors; a load inductor having a first end connected to a connecting point of said first and second Josephson junction elements and having a second end connected to a connecting point of said first and second excitation inductors; an input signal line coupled to said load inductor; and first and second resistors connected, respectively, to a first current path including at least said first Josephson junction element and a second current path including at least said second Josephson junction element thereby effecting suppression of unwanted resonance in the current paths, wherein said first and second current paths belonging to the circuit including said first and second Josephson elements, said first and second excitation inductors and said load inductor.

Claim 3

A superconducting switching circuit according to claim 1, wherein said first and second resistors are connected in parallel with said first and second Josephson junction elements, respectively.

Claim 4

A superconducting switching circuit according to claim 2, wherein each of said first and second Josephson junction elements comprises a first electrode, a second electrode having a first main side parallelly facing a first section of a main side of said first electrode, and an insulating film for forming a first barrier layer in contact with and being disposed between said first and second electrodes, each of said elements further comprising a third electrode having a first main side parallelly facing another section of said main side of said first electrode, and a second insulating film for forming a second barrier layer in contact with and being disposed between said first and third electrodes, said second insulating film having a sufficiently larger contact area than said first insulating film, and wherein each of said resistors comprises a fourth electrode for connecting said third electrode to said second electrode.

Claim 5

A superconducting switching circuit according to claim 1, wherein said first resistor is connected in parallel with said load inductor, said second resistor being connected in parallel with the whole or a part of the series connection of said first and second excitation inductors.

Claim 6

A memory cell comprising: first and second Josephson junction elements connected in series to each other, first and second excitation inductors connected in series to each other and each connected in series to a respective one of said first and second Josephson junction elements, said first and second excitation inductors being magnetically coupled to a select line; a first inductor having a first end coupled to a first connecting point of said first and second Josephson junction elements and having a second end connected to a second connecting point of said first and second excitation inductors; a third Josephson junction element disposed between said first and second connecting points and connected in series to said first inductor; means coupled to the serial connection of said first inductor and said third Josephson junction element for supplying a DC bias magnetic flux corresponding to a flux phase angle of π to said serial connection; and first, second and third resistors connected in parallel with said first, second and third Josephson junction elements, respectively, thereby effecting suppression of resonance oscillation in the current paths.

Claim 7

A memory cell comprising: first and second Josephson junction elements connected in series to each other, first and second excitation inductors connected in series to each other and each connected in series to a respective one of said first and second Josephson junction elements, said first and second excitation inductors being magnetically coupled to a select line; a first inductor having a first end coupled to a first connecting point of said first and second Josephson junction elements and having a second end connected to a second connecting point of said first and second excitation inductors; a third Josephson junction element disposed between said first and second connecting points and connected in series to said first inductor; means coupled to the serial connection of said first inductor and said third Josephson junction element for supplying a DC bias magnetic flux corresponding to a flux phase angle of π to said serial connection; and first, second and third resistors connected in parallel with said first, second and third Josephson junction elements, respectively, thereby effecting suppression of resonance oscillation in the current paths.

Claim 8

A memory cell according to claim 5, further including a second inductor connected in parallel with said serial connection of said first inductor and said third Josephson junction element, said second inductor being used for reading and writing of memory signals.

Claim 9

A memory cell according to claim 5, wherein said serial connection of said third Josephson junction element and said first inductor is directly connected to said first connecting point.

Claim 10

A memory cell according to claim 5, wherein said DC bias flux supplying means is disposed between said serial connection of said third Josephson junction element and said first inductor and said first junction.

Claim 11

A memory circuit comprising: a plurality of select lines; a plurality of data lines; a plurality of memory cells each connected to one of said select lines and one of said data lines; first and second lines of equal flux phase provided in common to said plurality of memory cells; and means for supplying DC magnetic fluxes corresponding to a relative flux phase difference angle of π to said first and second equal flux phase lines; wherein each of said memory cells comprises: first and second Josephson junction elements connected in series and each having an end, common to the series connected ends, for connection to said first equal flux phase line; first and second excitation inductors connected in series to said first and second Josephson elements and connected in series to each other, said first and second excitation inductors being magnetically coupled to one of said select lines; a serial connection of a first inductor and a third Josephson junction element, said serial connection being coupled between a connecting point of said first and second excitation inductors and said second equal flux phase line; a second inductor coupled between the common connection of said first and second excitation inductors and said first equal flux phase line, said second inductor being magnetically coupled to one of said data lines; and first, second and third resistors each respectively connected to a respective current path of said first, second and third Josephson junction elements.

Claim 12

A memory circuit comprising: a plurality of select lines; a plurality of data lines; a plurality of memory cells each connected to one of said select lines and one of said data lines; first and second lines of equal flux phase provided in common to said plurality of memory cells; and means for supplying DC magnetic fluxes corresponding to a relative flux phase difference angle of π to said first and second equal flux phase lines; wherein each of said memory cells comprises: first and second Josephson junction elements connected in series and each having an end, common to the series connected ends, for connection to said first equal flux phase line; first and second excitation inductors connected in series to said first and second Josephson elements and connected in series to each other, said first and second excitation inductors being magnetically coupled to one of said select lines; a serial connection of a first inductor and a third Josephson junction element, said serial connection being coupled between a connecting point of said first and second excitation inductors and said second equal flux phase line; a second inductor coupled between the common connection of said first and second excitation inductors and said first equal flux phase line, said second inductor being magnetically coupled to one of said data lines; and first, second and third resistors each respectively connected to a respective current path of said first, second and third Josephson junction elements.

Claim 13

A memory circuit according to claim 9, wherein said first, second and third resistors are connected in parallel with said first, second and third Josephson junction elements, respectively.

Claim 14

A memory circuit according to claim 9, further including an offset current source connected to a junction between said first and second excitation inductors in each of said memory cells for supplying an offset current corresponding to the difference in the maximum superconducting current between said first and second Josephson junction elements of each of said memory cells.

Claim 15

A composite combination comprising: a first electrode, a second electrode having a first main side parallelly facing a first section of a main side of said first electrode, an insulating film for forming a barrier layer in contact with and disposed between said first and second electrodes, a third electrode having a first main side parallelly facing another section of said main side of said first electrode, a second insulating film in contact with and being disposed between said first and third electrodes for forming a barrier layer having a sufficiently larger contact area than said first insulating film, and a fourth electrode for connecting said third electrode to said second electrode to serve as a resistor.

Claim 16

A composite combination comprising: a first electrode, a second electrode having a first main side parallelly facing a first section of a main side of said first electrode, an insulating film for forming a barrier layer in contact with and disposed between said first and second electrodes, a third electrode having a first main side parallelly facing another section of said main side of said first electrode, a second insulating film in contact with and being disposed between said first and third electrodes for forming a barrier layer having a sufficiently larger contact area than said first insulating film, and a fourth electrode for connecting said third electrode to said second electrode to serve as a resistor.

Claim 17

A superconducting switching circuit comprising: first and second Josephson junction elements connected in series; first and second excitation inductors connected in series to each other and connected in series to said first and second Josephson junction elements; an exciting line magnetically coupled to said first and second excitation inductors; a load inductor having a first end connected to a connecting point of said first and second Josephson junction elements and having a second end connected to a connecting point of said first and second excitation inductors; an input signal line coupled to said load inductor; and first and second resistors respectively connected in parallel with said first and second Josephson junction elements, wherein first and second paths are formed in the circuit including said first and second Josephson elements in parallel with said first and second resistors, said first and second excitation inductors and said load inductor, wherein each of said first and second Josephson junction elements comprises a first electrode, a second electrode having a first main side parallelly facing a main side of said first electrode, and an insulating film for forming a first barrier layer in contact with and being disposed between said first and second electrodes, each of said elements further comprising a third electrode having a first main side parallelly facing another section of said main side of said first electrode, and a second insulating film for forming a second barrier layer in contact with and being disposed between said first and third electrodes, said second insulating film having a sufficiently larger contact area than said first insulating film, and wherein each of said resistors comprises a fourth electrode for connecting said third electrode to said second electrode.

Claim 18

A superconducting switching circuit comprising: first and second Josephson junction elements connected in series; first and second excitation inductors connected in series to each other and connected in series to said first and second Josephson junction elements; an exciting line magnetically coupled to said first and second excitation inductors; a load inductor having a first end connected to a connecting point of said first and second Josephson junction elements and having a second end connected to a connecting point of said first and second excitation inductors; an input signal line coupled to said load inductor; and first and second resistors respectively connected in parallel with said first and second Josephson junction elements, wherein first and second paths are formed in the circuit including said first and second Josephson elements in parallel with said first and second resistors, said first and second excitation inductors and said load inductor, wherein each of said first and second Josephson junction elements comprises a first electrode, a second electrode having a first main side parallelly facing a main side of said first electrode, and an insulating film for forming a first barrier layer in contact with and being disposed between said first and second electrodes, each of said elements further comprising a third electrode having a first main side parallelly facing another section of said main side of said first electrode, and a second insulating film for forming a second barrier layer in contact with and being disposed between said first and third electrodes, said second insulating film having a sufficiently larger contact area than said first insulating film, and wherein each of said resistors comprises a fourth electrode for connecting said third electrode to said second electrode.

Claim 19

A superconducting switching circuit comprising: first and second Josephson junction elements connected in series; first and second excitation inductors connected in series to each other and connected in series to said first and second Josephson junction elements; an exciting line magnetically coupled to said first and second excitation inductors; a load inductor having a first end connected to a connecting point of said first and second Josephson junction elements and having a second end connected to a connecting point of said first and second excitation inductors; an input signal line coupled to said load inductor; and first and second resistors connected, respectively, to a first current path including at least said first Josephson junction element and a second current path including at least said second Josephson junction element, said first and second paths belonging to the circuit including said first and second Josephson elements, said first and second excitation inductors and said load inductor, wherein each of said first and second Josephson junction elements comprises a first electrode, a second electrode having a first main side parallelly facing a first section of a main side of said first electrode, and an insulating film for forming a first barrier layer in contact with and being disposed between said first and second electrodes, each of said elements further comprising a third electrode having a first main side parallelly facing another section of said main side of said first electrode, and a second insulating film for forming a second barrier layer in contact with and being disposed between said first and third electrodes, said second insulating film having a sufficiently larger contact area than said first insulating film, and wherein each of said resistors comprises a fourth electrode for connecting said third electrode to said second electrode.

Claim 20

A superconducting switching circuit comprising: first and second Josephson junction elements connected in series; first and second excitation inductors connected in series to each other and connected in series to said first and second Josephson junction elements; an exciting line magnetically coupled to said first and second excitation inductors; a load inductor having a first end connected to a connecting point of said first and second Josephson junction elements and having a second end connected to a connecting point of said first and second excitation inductors; an input signal line coupled to said load inductor; and first and second resistors connected, respectively, to a first current path including at least said first Josephson junction element and a second current path including at least said second Josephson junction element, said first and second paths belonging to the circuit including said first and second Josephson elements, said first and second excitation inductors and said load inductor, wherein each of said first and second Josephson junction elements comprises a first electrode, a second electrode having a first main side parallelly facing a first section of a main side of said first electrode, and an insulating film for forming a first barrier layer in contact with and being disposed between said first and second electrodes, each of said elements further comprising a third electrode having a first main side parallelly facing another section of said main side of said first electrode, and a second insulating film for forming a second barrier layer in contact with and being disposed between said first and third electrodes, said second insulating film having a sufficiently larger contact area than said first insulating film, and wherein each of said resistors comprises a fourth electrode for connecting said third electrode to said second electrode.

Claim 21

A superconducting switching circuit comprising: first and second Josephson junction elements connected in series; first and second excitation inductors connected in series to each other and connected in series to said first and second Josephson junction elements; an exciting line magnetically coupled to said first and second excitation inductors; a load inductor having a first end connected to a connecting point of said first and second Josephson junction elements and having a second end connected to a connecting point of said first and second excitation inductors; an input signal line coupled to said load inductor; and first and second resistors, said first resistor being connected in parallel with said load inductor and said second resistor being connected in parallel with the whole or a part of the series connection of said first and second excitation inductors.

Claim 22

A superconducting switching circuit comprising: first and second Josephson junction elements connected in series; first and second excitation inductors connected in series to each other and connected in series to said first and second Josephson junction elements; an exciting line magnetically coupled to said first and second excitation inductors; a load inductor having a first end connected to a connecting point of said first and second Josephson junction elements and having a second end connected to a connecting point of said first and second excitation inductors; an input signal line coupled to said load inductor; and first and second resistors, said first resistor being connected in parallel with said load inductor and said second resistor being connected in parallel with the whole or a part of the series connection of said first and second excitation inductors.

Claim 23

A superconducting switching circuit according to claim 15, wherein said second resistor being connected in parallel with the series connection of said first and second excitation inductors.