US4787352A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Engine control circuit including speed monitor and governor
Assignee: Bankers Trust Co
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Filing: 1987-08-06
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Granted: 1988-11-29
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Expires: 2007-08-06
Abstract
Abstract A monitor and governor circuit provides speed control for an engine. The governor portion of the circuit, principally a PID controller, includes a fail safe circuit to shut the engine down in the absence of signals related to engine RPM. In addition, the governor includes a high gain feature operable during start up to keep the integrator from saturating. The speed monitor portion of the circuit prevents engine damage in the event that the speed governor should fail as, for example, due to a shorted output transistor or an open speed setting potentiometer. The end user is not required to set the speed monitor since it can be preset to a selected percent of the governor set speed.
Inventors
- 👤 George Anderson
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 06:30
CPC Classifications
F; F02; F02D; F02D31/00; F02D31/001; F02D31/007; F02D31/009; F02D41/00; F02D41/02; F02D41/04; F02D41/06; F02D41/062; F02D41/22; Y; Y02; Y02T; Y02T10/00; Y02T10/10; Y02T10/40
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
146 words
A control circuit for an internal combustion engine comprising: (a) buffer means receiving a signal related to engine RPM (the RPM signal) and producing a buffered signal proportional thereto; (b) a PID governor circuit for receiving and comparing the buffered signal against a reference signal to control the speed of said engine as a result of said comparison, said PID governor circuit including: (i) operational amplifiers receiving said buffered signal for producing an error signal and a proportional (P), integral (I), and a derivative (D) of said error signal, the P, I, D signals being combined to produce a signal for controlling engine speed; and (ii) means for providing high gain for the operational amplifiers producing the P and D signals during engine start up to permit the engine to quickly reach normal operating speed and avoid saturation of the operational amplifier producing the I signal.
Claim 2
Dependent Claim
146 words
A control circuit for an internal combustion engine comprising: (a) buffer means receiving a signal related to engine RPM (the RPM signal) and producing a buffered signal proportional thereto; (b) a PID governor circuit for receiving and comparing the buffered signal against a reference signal to control the speed of said engine as a result of said comparison, said PID governor circuit including: (i) operational amplifiers receiving said buffered signal for producing an error signal and a proportional (P), integral (I), and a derivative (D) of said error signal, the P, I, D signals being combined to produce a signal for controlling engine speed; and (ii) means for providing high gain for the operational amplifiers producing the P and D signals during engine start up to permit the engine to quickly reach normal operating speed and avoid saturation of the operational amplifier producing the I signal.
Claim 3
Dependent Claim
32 words
A control circuit according to claim 1 wherein said PID governor circuit includes means for providing high gain during engine start up to permit the engine to quickly reach normal operating speed.
Claim 4
Dependent Claim
31 words
A control circuit according to claim 1 wherein said fail safe circuit means includes means for grounding the input to said PID governor circuit in the absence of the RPM signal.
Claim 5
Dependent Claim
50 words
A control circuit in accordance with claim 1 further including a speed monitor circuit for detecting fault conditions and shutting down the engine, said speed monitor circuit including: (a) means for detecting the absence of the RPM signal during engine start up; (b) means for detecting a faulty reference signal.
Claim 6
Dependent Claim
113 words
A control circuit for an integral combustion engine comprising: (a) buffer means receiving a signal related to engine RPM (the RPM signal) and producing a buffered signal proportional thereto; (b) a PID governor circuit for receiving and comparing the buffered signal against a reference signal to control the speed of said engine as a result of said comparison; (c) said buffer means including fail safe circuit means for causing said PID governor circuit to shut down the engine if no RPM signal is detected; and (d) a speed monitor circuit for shutting down the engine upon detecting an overspeed condition in which the buffered signal exceeds said reference signal by a selectable percentage.
Claim 7
Dependent Claim
113 words
A control circuit for an integral combustion engine comprising: (a) buffer means receiving a signal related to engine RPM (the RPM signal) and producing a buffered signal proportional thereto; (b) a PID governor circuit for receiving and comparing the buffered signal against a reference signal to control the speed of said engine as a result of said comparison; (c) said buffer means including fail safe circuit means for causing said PID governor circuit to shut down the engine if no RPM signal is detected; and (d) a speed monitor circuit for shutting down the engine upon detecting an overspeed condition in which the buffered signal exceeds said reference signal by a selectable percentage.
Claim 8
Dependent Claim
141 words
A control circuit for an internal combustion engine comprising: (a) buffer means receiving a signal related to engine RPM (the RPM signal) and producing a buffered signal proportional thereto; (b) a PID governor circuit for receiving and comparing the buffered signal against a reference signal to control the speed of said engine as a result of said comparison; (c) said buffer means including fail safe circuit means for causing said PID governor circuit to shut down the engine if no RPM signal is detected; and (d) a speed monitor circuit for shutting down the engine upon detecting an overspeed condition in which the buffered signal exceeds said reference signal by a selectable percentage said speed monitor circuit further includes: (i) means for detecting the absence of the RPM signal during start up; and (ii) means for detecting a faulty reference signal.
Claim 9
Dependent Claim
141 words
A control circuit for an internal combustion engine comprising: (a) buffer means receiving a signal related to engine RPM (the RPM signal) and producing a buffered signal proportional thereto; (b) a PID governor circuit for receiving and comparing the buffered signal against a reference signal to control the speed of said engine as a result of said comparison; (c) said buffer means including fail safe circuit means for causing said PID governor circuit to shut down the engine if no RPM signal is detected; and (d) a speed monitor circuit for shutting down the engine upon detecting an overspeed condition in which the buffered signal exceeds said reference signal by a selectable percentage said speed monitor circuit further includes: (i) means for detecting the absence of the RPM signal during start up; and (ii) means for detecting a faulty reference signal.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-11-29 | 1992-05-30 | 1992-11-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-11-29 | 1996-05-30 | 1996-11-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-11-29 | 2000-05-30 | 2000-11-29 | $7700.00 | Window Closed / Lapsed |