Stacked semiconductor device

Claim 2

A stacked semiconductor device comprising: a first semiconductor layer having formed at least partially therein a first plurality of active integrated circuit elements containing a large number of circuit elements and at least one additional coplanar complete active integrated circuit having a relatively high heat generating capacity to thereby provide said stacked semiconductor device with an improved heat dissipating ability, said first plurality of elements and said one additional circuit forming a first integrated circuit; an insulating layer formed upon and continuously and uniformly contacting and covering all of said first plurality of elements and leaving exposed all of said one additional circuit; and a second semiconductor layer formed upon and continuously and uniformly covering and contacting said insulating layer and leaving exposed all of said one additional integrated circuit and having formed at least partially therein a second plurality of active integrated circuit elements, said second plurality of elements forming a second integrated circuit.

Claim 3

A stacked semiconductor device as recited in claim 1, wherein said second semiconductor layer further contacts a portion of said first semiconductor layer.

Claim 4

A stacked semiconductor device according to claim 1, each of the first and second integrated circuits being made of more than one layer.

Claim 5

A stacked semiconductor device as recited in claim 1, wherein said second semiconductor layer has a contacting portion in contact with said first semiconductor layer at a location between said one additional circuit and said first plurality of active integrated circuit elements and is recrystallized in situ from said contacting portion.

Claim 6

A stacked semiconductor device comprising: a first semiconductor layer having formed at least partially therein a first plurality of active integrated circuit elements containing a large number of circuit elements and at least one additional coplanar complete active integrated circuit having a relatively high heat generating capacity to thereby provide said stacked semiconductor device with an improved heat dissipating ability, said first plurality of elements and said one additional circuit forming a first integrated circuit; an insulating layer formed upon and continuously and uniformly contacting and covering all of said first plurality of elements and leaving exposed all of said one additional circuit; a second semiconductor layer formed upon and continuously and uniformly covering and contacting said insulating layer and leaving exposed all of said one additional integrated circuit and having formed at least partially therein a second plurality of active integrated circuit elements, said second plurality of elements forming a second integrated circuit; and at least one further stacked layer formed over said second semiconductor layer, and including a portion formed over said first plurality of active integrated circuit elements but being spaced therefrom.

Claim 7

A stacked semiconductor device comprising: a first semiconductor layer having formed at least partially therein a first plurality of active integrated circuit elements containing a large number of circuit elements and at least one additional coplanar complete active integrated circuit having a relatively high heat generating capacity to thereby provide said stacked semiconductor device with an improved heat dissipating ability, said first plurality of elements and said one additional circuit forming a first integrated circuit; an insulating layer formed upon and continuously and uniformly contacting and covering all of said first plurality of elements and leaving exposed all of said one additional circuit; a second semiconductor layer formed upon and continuously and uniformly covering and contacting said insulating layer and leaving exposed all of said one additional integrated circuit and having formed at least partially therein a second plurality of active integrated circuit elements, said second plurality of elements forming a second integrated circuit; and at least one further stacked layer formed over said second semiconductor layer, and including a portion formed over said first plurality of active integrated circuit elements but being spaced therefrom.

Claim 8

A stacked semiconductor device according to claim 5, a heat dissipation region being formed between an exposed surface of said first semiconductor layer and a confronting surface of said portion formed over said first plurality of active integrated circuit elements.