Semiconductor integrated circuit formed on an insulator substrate

Claim 1

A semiconductor integrated circuit with temperature compensation, comprising an enhancement-depletion semiconductor integrated circuit containing a silicon on sapphire substrate including a drive transistor of an enhancement type and a load transistor of a depletion type, said depletion type load transistor including a channel region having a layer of insulator material thereon, thereby to define an insulated gate depletion mode transistor, said depletion mode channel region having a donor concentration N D in the range of 2×10 13 -3.6×10 15 /cm 3 and said depletion mode gate insulator having a surface charge Q ss that has a substantially constant value of about 8×10 -9 coulomb/cm 2 ·eV at a temperature of about 20° C., said depletion type load transistor having a threshold voltage between -2.1V and -1.7V when the ambient temperature of said circuit is in the range of -60° C. to 60° C., and said circuit having a variation rate of delay time t pd and power consumption P d at a substantially constant value within about 10%, thereby significantly reducing temperature dependency of the delay time and power consumption.