US4803659A
Expired / Lapsed
US
⏱️ 0.0 years remaining
EPROM latch circuit
Assignee: Intel Corp
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Filing: 1987-01-22
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Granted: 1989-02-07
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Expires: 2007-01-22
Abstract
Abstract A latch circuit provides for a reading of a state of an EPROM cell and retains that state after the reading sequence is completed. The memory state of the EPROM is inputted to a NOR gate during a power on reset condition. The output of the NOR gate is fed back through an inverter to the input of the NOR gate, such that when the EPROM is deactivated, the input of the NOR gate is latched to the previous EPROM memory state.
Inventors
- 👤 Kirby S. Hallenbeck
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 22:30
CPC Classifications
G; G11; G11C; G11C17/00; G11C16/00; G11C16/02; G11C16/06; G11C16/10; G11C16/20; G11C16/26
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
180 words
A circuit for latching a state of a memory, comprising: a first gating means coupled to said memory for reading said state of said memory; said first gating means also coupled to receive an enabling signal which activates said reading of said memory; said first gating means further coupled to the output of a feedback means and to the input of a second gating means; said second gating means having a first input, said first input being coupled to said first gating means for receiving said state of said memory when said first gating means is activated; said second gating means having a second input, said second input coupled to a reset signal; said second gating means having an output, said output being determined by said state of said memory once said reset signal is deactivated; said feedback means coupled to said output and said first input of said second gating means to latch said first input to said memory state, such that when said first gating means is deactivated, said input is latched to coincide with said memory state.
Claim 2
Dependent Claim
180 words
A circuit for latching a state of a memory, comprising: a first gating means coupled to said memory for reading said state of said memory; said first gating means also coupled to receive an enabling signal which activates said reading of said memory; said first gating means further coupled to the output of a feedback means and to the input of a second gating means; said second gating means having a first input, said first input being coupled to said first gating means for receiving said state of said memory when said first gating means is activated; said second gating means having a second input, said second input coupled to a reset signal; said second gating means having an output, said output being determined by said state of said memory once said reset signal is deactivated; said feedback means coupled to said output and said first input of said second gating means to latch said first input to said memory state, such that when said first gating means is deactivated, said input is latched to coincide with said memory state.
Claim 3
Dependent Claim
15 words
The circuit of claim 1, wherein said memory is comprised of an electrically programmable read-only-memory.
Claim 4
Dependent Claim
16 words
The circuit of claim 2, wherein said second gating means is comprised of a NOR gate.
Claim 5
Dependent Claim
12 words
The circuit of claim 3, wherein said feedback means is an inverter.
Claim 6
Dependent Claim
16 words
The circuit of claim 4, wherein said first gating means is comprised of a field-effect transistor.
Claim 7
Dependent Claim
204 words
A circuit for latching a bit state of an electrically programmable read only memory (EPROM) cell onto a bit line, comprising: first gating means coupled to said EPROM memory cell for reading said state of said memory cell; said first gating means also coupled to receive an enabling signal which activates said reading of said EPROM memory cell; second gating means having a first input, a second input and an output; said first input being coupled to said first gating means for receiving said state of said EPROM memory cell when said first gating means is activated; said second input coupled to receive a power on reset signal; said output coupled to said bit line, said output being determined by said state of said memory on said first input when said power on reset signal is deactivated; a feedback loop coupled to said first input and output for latching said first input to said memory state of said EPROM memory cell, such that when said first gating means is deactivated after said power on reset signal is deactivated, said first input is latched to said output to coincide with said state of said EPROM memory cell and said memory is deactivated to conserve power.
Claim 8
Dependent Claim
204 words
A circuit for latching a bit state of an electrically programmable read only memory (EPROM) cell onto a bit line, comprising: first gating means coupled to said EPROM memory cell for reading said state of said memory cell; said first gating means also coupled to receive an enabling signal which activates said reading of said EPROM memory cell; second gating means having a first input, a second input and an output; said first input being coupled to said first gating means for receiving said state of said EPROM memory cell when said first gating means is activated; said second input coupled to receive a power on reset signal; said output coupled to said bit line, said output being determined by said state of said memory on said first input when said power on reset signal is deactivated; a feedback loop coupled to said first input and output for latching said first input to said memory state of said EPROM memory cell, such that when said first gating means is deactivated after said power on reset signal is deactivated, said first input is latched to said output to coincide with said state of said EPROM memory cell and said memory is deactivated to conserve power.
Claim 9
Dependent Claim
17 words
The circuit of claim 6, wherein said second gating means is comprised of a CMOS NOR gate.
Claim 10
Dependent Claim
12 words
The circuit of claim 7, wherein said feedback loop includes an inverter.
Claim 11
Dependent Claim
16 words
The circuit of claim 8, wherein said first gating means is comprised of a field-effect transitor.
Claim 12
Dependent Claim
16 words
The circuit of claim 9, wherein a plurality of EPROM cells are coupled to said circuit.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-02-07 | 1992-08-08 | 1993-02-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-02-07 | 1996-08-08 | 1997-02-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-02-07 | 2000-08-08 | 2001-02-07 | $7700.00 | Window Closed / Lapsed |