US4809232A
Expired / Lapsed
US
⏱️ 0.0 years remaining
High speed, very large (8 megabyte) first in/first out buffer memory (FIFO)
Assignee: GOVERNMENT OF UNITED STATES ENERGY THE, Department of
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Filing: 1986-12-16
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Granted: 1989-02-28
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Expires: 2006-12-16
Abstract
Abstract A fast FIFO (First In First Out) memory buffer capable of storing data at rates of 100 megabytes per second. The invention includes a data packer which concatenates small bit data words into large bit data words, a memory array having individual data storage addresses adapted to store the large bit data words, a data unpacker into which large bit data words from the array can be read and reconstructed into small bit data words, and a controller to control and keep track of the individual data storage addresses in the memory array into which data from the packer is being written and data to the unpacker is being read.
Inventors
- 👤 Alan E. Baumbaugh
- 👤 Kelly L. Knickerbocker
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 14:12
CPC Classifications
G; G06; G06F; G06F5/00; G06F5/06; G06F5/08
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
257 words
A buffer system for storing a stream of data words from a data source and retrieving the data words for delivery to a data processing system comprising: data packer means for forming a series of (P×M×N)-bit data words from a series, of (P×M) N-bit data words, said data packer means adapted to receive the data words from the data source; memory array means coupled to said data packer means and responsive to the formation of said series of words to receive at least (P×M×N)-bit data words from said data packer means, said memory array means having a plurality of individual data storage addresses for storing said series of (P×M×N)-bit data words; data unpacker means coupled to said memory array means and adapted to selectively receive (P×M×N)-bit data words from said memory array means for sequentially forming a series of N-bit data words from a corresponding series of (P×M×N)-bit data words stored in said memory array, for transmission to a data processing system; control means coupled to said data packer means, said memory array means and said data unpacker means for controlling the transfer of P (M×N) bit data words into and through said data packer means, controlling the transfer of (P×M×N)-bit data words from said data packer means into individual storage addresses of said memory array means, controlling the transfer of (P×M×N)-bit data words from the individual storage addresses of said memory array means to said data unpacker means, and controlling the transfer of P (M×N) bit data words through and out of said data unpacker means.
Claim 2
Dependent Claim
257 words
A buffer system for storing a stream of data words from a data source and retrieving the data words for delivery to a data processing system comprising: data packer means for forming a series of (P×M×N)-bit data words from a series, of (P×M) N-bit data words, said data packer means adapted to receive the data words from the data source; memory array means coupled to said data packer means and responsive to the formation of said series of words to receive at least (P×M×N)-bit data words from said data packer means, said memory array means having a plurality of individual data storage addresses for storing said series of (P×M×N)-bit data words; data unpacker means coupled to said memory array means and adapted to selectively receive (P×M×N)-bit data words from said memory array means for sequentially forming a series of N-bit data words from a corresponding series of (P×M×N)-bit data words stored in said memory array, for transmission to a data processing system; control means coupled to said data packer means, said memory array means and said data unpacker means for controlling the transfer of P (M×N) bit data words into and through said data packer means, controlling the transfer of (P×M×N)-bit data words from said data packer means into individual storage addresses of said memory array means, controlling the transfer of (P×M×N)-bit data words from the individual storage addresses of said memory array means to said data unpacker means, and controlling the transfer of P (M×N) bit data words through and out of said data unpacker means.
Claim 3
Dependent Claim
18 words
The buffer system of claim 1 where said memory array means is a semiconductor random access memory (RAM).
Claim 4
Dependent Claim
29 words
The buffer system of claim 1 where said memory array means is dynamic metal oxide semiconductor RAM and said control means includes means for refreshing said memory array means.
Claim 5
Dependent Claim
34 words
The buffer system of claim 3 where said data packer means and said memory array means are sized to store at least 10 8 , 8-bit data words from a data source per second.
Claim 6
Dependent Claim
63 words
The buffer system of claim 4 further including a temporary storage latch sized to store at least (M×N) binary digits, operatively connected between said data packer means and said memory array means to receive data words from said data packer means for temporarily holding (M×N)-bit data words from said data packer means until said memory array means is available to store data words.
Claim 7
Dependent Claim
49 words
The buffer system of claim 4 including a temporary storage latch sized to store at least (M×N)-binary digits, operatively connected between said memory array means and said data unpacker means, to receive data words from said memory array means for temporarily storing (M×N)-bit data words for said data unpacker.
Claim 8
Dependent Claim
63 words
The buffer system of claim 4 including a first temporary storage latch sized to store at least (M×N)-binary digits, said first latch operatively connected between said data packer means and said memory array means and a second temporary storage latch sized to store at least (M×N) binary digits, said second latch operatively connected between said memory array means and said data unpacker means.
Claim 9
Dependent Claim
26 words
The buffer system of claim 1 where said data packer means and said data unpacker means are comprised of a plurality of N-bit data latch circuits.
Claim 10
Dependent Claim
33 words
The buffer system of claim 1 where said control means controls the transfer of data through said data packer means, said memory array means and said data unpacker means on a last-in/first-out basis.
Claim 11
Dependent Claim
33 words
The buffer system of claim 1 where said control means controls the transfer of data through said data packer means, said memory array means and said data unpacker means on a first-in/first-out basis.
Claim 12
Independent Claim
112 words
A method of storing and retrieving a high-speed stream of (P×N) N-bit data words comprising the steps of: conducting the stream of(P×M), N-bit data words into a data packer to form a series of (P×M×N)-bit data words corresponding to said (P×M), N-bit data words, storing said (P×M×N)-bit data words in a memory array at individual data storage addresses in said memory array sized to receive said (P×M×)-bit data words; retrieving said (P×M×N)-bit data words from the individual data storage addresses of said memory array and conducting said stream of (P×M×N)-bit data words into a data unpacker to reform said stream of M, N-bit data words for use by the data processing software.
Claim 13
Independent Claim
112 words
A method of storing and retrieving a high-speed stream of (P×N) N-bit data words comprising the steps of: conducting the stream of(P×M), N-bit data words into a data packer to form a series of (P×M×N)-bit data words corresponding to said (P×M), N-bit data words, storing said (P×M×N)-bit data words in a memory array at individual data storage addresses in said memory array sized to receive said (P×M×)-bit data words; retrieving said (P×M×N)-bit data words from the individual data storage addresses of said memory array and conducting said stream of (P×M×N)-bit data words into a data unpacker to reform said stream of M, N-bit data words for use by the data processing software.
References Cited (Backward Citations)
US4733376A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-02-28 | 1992-08-29 | 1993-02-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-02-28 | 1996-08-29 | 1997-02-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-02-28 | 2000-08-29 | 2001-02-28 | $7700.00 | Window Closed / Lapsed |