US4811067A
Expired / Lapsed
US
⏱️ 0.0 years remaining
High density vertically structured memory
Assignee: International Business Machines Corp
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Filing: 1986-05-02
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Granted: 1989-03-07
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Expires: 2006-05-02
Abstract
Abstract A dynamic random access memory is provided wherein each cell has a storage capacitor and switching device and a bit/sense line or plate located along a sidewall of a trench formed in a semiconductor substrate. In a more particular structure of the cell, the trench width defines the length of the switching device, with the storage capacitor and a highly conductive bit/sense line being formed along opposite sidewalls of the trench. In an array of such cells, the highly conductive bit/sense line or plane interconnecting a large number of the cells of the array extends continuously from cell to cell within the trench at a sidewall thereof. Likewise, the storage capacitors of these many cells have a highly conductive common plate extending continuously within the trench at the opposite sidewall.
Inventors
- 👤 Brian F. Fitzgerald
- 👤 Kim Y. T. Nguyen
- 👤 Son V. Nguyen
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 09:17
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/403; G11C11/404; H; H10; H10B; H10B12/00; H10B12/30; H10B12/37
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
148 words
A memory array comprising a semiconductor substrate having a first type conductivity and having a plurality of parallelly-arranged trenches and a plurality of elongated isolation regions arranged in a direction orthogonal to the direction of said trenches so as to define a plurality of cell regions, a plurality of memory cells, each of said cells being disposed within a respective one of said cell regions, each of said cells including a transistor having a diffusion region of a second type conductivity disposed on a given sidewall of a respective one of said trenches and a storage capacitor coupled to said diffusion region through said transistor and a plurality of conductive lines, each line being disposed substantially entirely within a respective one of said trenches along said given sidewall and in electrical contact with a plurality of said diffusion regions disposed on said given sidewall in said respective trench.
Claim 2
Dependent Claim
148 words
A memory array comprising a semiconductor substrate having a first type conductivity and having a plurality of parallelly-arranged trenches and a plurality of elongated isolation regions arranged in a direction orthogonal to the direction of said trenches so as to define a plurality of cell regions, a plurality of memory cells, each of said cells being disposed within a respective one of said cell regions, each of said cells including a transistor having a diffusion region of a second type conductivity disposed on a given sidewall of a respective one of said trenches and a storage capacitor coupled to said diffusion region through said transistor and a plurality of conductive lines, each line being disposed substantially entirely within a respective one of said trenches along said given sidewall and in electrical contact with a plurality of said diffusion regions disposed on said given sidewall in said respective trench.
Claim 3
Dependent Claim
24 words
A memory array as set forth in claim 1 wherein said conductive lines are metallic plates disposed in physical contact with said diffusion regions.
Claim 4
Dependent Claim
25 words
A memory array as set forth in claim 2 wherein said storage capacitors are disposed on sidewalls of said trenches opposite to said given sidewalls.
Claim 5
Dependent Claim
34 words
A memory array as set forth in claim 3 wherein said transistors are field effect transistors having gate electrodes disposed at the bottom of said trenches and separated therefrom by a layer of insulation.
Claim 6
Dependent Claim
33 words
A memory array as set forth in claim 4 further including a plurality of parallelly-arranged word lines disposed in a direction orthogonal to the direction of said trenches and contacting said gate electrodes.
Claim 7
Dependent Claim
28 words
A memory array as set forth in claim 1 wherein each of said isolation regions includes a given trench formed in said semiconductor substrate filled with insulating material.
Claim 8
Dependent Claim
32 words
A memory array as set forth in claim 5 wherein each of said word lines and the gate electrodes contacting the respective word line is an integral structure made of doped polysilicon.
Claim 9
Dependent Claim
47 words
A memory array as set forth in claim 7 further including a second plurality of conductive lines, each of said second conductive lines being disposed within a respective trench on the sidewall thereof opposite to said given sidewall and connected to a plurality of said storage capacitors.
Claim 10
Dependent Claim
18 words
A memory array as set forth in claim 8 wherein said second pluralilty of lines are metallic films.
Claim 11
Dependent Claim
18 words
A memory array as set forth in claim 8 wherein said conductive lines are made of titanium silicide.
Claim 12
Dependent Claim
18 words
A memory array as set forth in claim 8 wherein said conductive lines are made of copper-doped aluminum.
Claim 13
Dependent Claim
17 words
A memory array as set forth in claim 8 wherein said conductive lines are made of tungsten.
Claim 14
Dependent Claim
30 words
A memory array as set forth in claim 5 wherein said gate electrodes and said word lines are made of titanium silicide and said semiconductor substrate is made of silicon.
Claim 15
Dependent Claim
22 words
A memory array as set forth in claim 6 wherein said insulating material includes segments of silicon dioxide and segments of polyimide.
References Cited (Backward Citations)
US3387286A
Cited
US3811076A
Cited
US3841926A
Cited
US4225945A
Cited
US4222062A
Cited
US4199772A
Cited
US4276557A
Cited
US4462040A
Cited
US4271418A
Cited
US4327476A
Cited
US4295924A
Cited
US4335450A
Cited
WO1981003241A1
Cited
US4364074A
Cited
US4663832A
Cited
US4689113A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-03-06 | 1992-09-05 | 1993-03-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-03-06 | 1996-09-05 | 1997-03-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-03-06 | 2000-09-05 | 2001-03-07 | $7700.00 | Window Closed / Lapsed |