High speed serial input/output semiconductor memory

Claim 2

A semiconductor memory comprising: a memory array including a plurality of memory cells for storing data; first data holding means for receiving data read out from said memory array through a first switching circuit; and second data holding means for receiving data read out form said memory array through a second switching circuit, the output of said second data holding means being transmitted to said first data holding means through a third switching circuit; wherein, in a random-access output operation, said first switching circuit is closed, while at least either one of said second and third switching circuits is opened, whereby said read data is output through said first data holding means, and wherein, in a serial output operation, said first switching circuit is opened, while said second switching means is closed and said third switching circuit is opened and closed at a predetermined timing, whereby said plurality of read data are output serially through said first and second data holding means.

Claim 3

A semiconductor memory according to claim 1, wherein the data read out from said memory array is constituted by a plurality of bits which are read out in parallel, said first, second and third switching circuits and said first and second data holding means being provided in correspondence with each of the bits constituting said data.

Claim 4

A semiconductor memory comprising; a memory array having a plurality of word lines, a plurality of data lines and memory cells respectively coupled between said word and data lines; an amplifier circuit for amplifying data read out from said memory array; a common data line provided between said memory array and said amplifier circuit; first selecting means for selecting said word lines on the basis of a row address signal; second selecting means for selectively connecting said data lines to said common data line on the basis of a column address signal; first data holding means for receiving an output signal form said amplifier circuit through a first switching circuit; second data holding means for receiving an output signal from said amplifier circuit through a second switching circuit, the output of said second data holding means being transmitted to said first data holding means through a third switching circuit; and a signal generating circuit forming an address signal which is supplied to said second selecting means; wherein, in a random-access output operation, said first switching circuit is closed, while at least either one of said second and third switching circuits is opened, whereby the output of said amplifier circuit is output through said first data holding means, and wherein, in a serial output operation, said second selecting means in response to the operation of said signal generating circuit sequentially connect said plurality of data lines to said common data line, and said first switching circuit is opened, while said second switching means is closed and said third switching circuit is opened and closed at a predetermined timing, whereby a plurality of outputs of said amplifier circuit are output serially through said first and second data holding means.

Claim 5

A semiconductor memory comprising; a memory array having a plurality of word lines, a plurality of data lines and memory cells respectively coupled between said word and data lines; an amplifier circuit for amplifying data read out from said memory array; a common data line provided between said memory array and said amplifier circuit; first selecting means for selecting said word lines on the basis of a row address signal; second selecting means for selectively connecting said data lines to said common data line on the basis of a column address signal; first data holding means for receiving an output signal form said amplifier circuit through a first switching circuit; second data holding means for receiving an output signal from said amplifier circuit through a second switching circuit, the output of said second data holding means being transmitted to said first data holding means through a third switching circuit; and a signal generating circuit forming an address signal which is supplied to said second selecting means; wherein, in a random-access output operation, said first switching circuit is closed, while at least either one of said second and third switching circuits is opened, whereby the output of said amplifier circuit is output through said first data holding means, and wherein, in a serial output operation, said second selecting means in response to the operation of said signal generating circuit sequentially connect said plurality of data lines to said common data line, and said first switching circuit is opened, while said second switching means is closed and said third switching circuit is opened and closed at a predetermined timing, whereby a plurality of outputs of said amplifier circuit are output serially through said first and second data holding means.

Claim 6

A semiconductor memory according to claim 3, wherein said signal generating circuit forms an address signal to supply said second selecting means in response to a control signal supplied from an external terminal.

Claim 7

A semiconductor memory according to claim 4, wherein said signal generating circuit is defined by a counter circuit which performs a step-up operation in response to a control signal supplied from an external terminal, the initial value for said counter circuit being given as a column address signal.

Claim 8

A semiconductor memory according to claim 4, wherein a signal for controlling said second switching circuit and a timing signal in response to which said second selecting means selectively connects said data lines to said common data line are formed on the basis of said control signal.

Claim 9

A semiconductor memory according to claim 3, wherein said memory cells are of the dynamic type, said amplifier circuit and said first and second data holding means being respectively constituted by static type circuits, said row and column address signals are respectively supplied from external terminals which are independent of each other, data read out from said memory array is constituted by a plurality of bits which are read out in parallel, and said amplifier circuit, said first, second and third switching circuits and said first and second data holding means are provided in correspondence with each of the bits constituting said data.

Claim 10

A semiconductor memory comprising: a memory array including a plurality of memory cells for storing data; first data holding means for receiving data read out from said memory array through a first switching circuit, said data being constituted by a plurality of bits which are read out in parallel, and said first switching circuit and said first data holding means being provided in correspondence with each of the bits constituting said data; and second data holding means for providing data output to said first data holding means from a second switching circuit, said second switching circuit and said second data holding means being provided in correspondence with each of the bits constituting said data; wherein said first and second switching circuits are opened and closed at a predetermined timing, whereby a plurality of data read out from said memory array are output serially through said first and second data holding means.

Claim 11

A semiconductor memory comprising: a memory array including a plurality of memory cells for storing data; first data holding means for receiving data read out from said memory array through a first switching circuit, said data being constituted by a plurality of bits which are read out in parallel, and said first switching circuit and said first data holding means being provided in correspondence with each of the bits constituting said data; and second data holding means for providing data output to said first data holding means from a second switching circuit, said second switching circuit and said second data holding means being provided in correspondence with each of the bits constituting said data; wherein said first and second switching circuits are opened and closed at a predetermined timing, whereby a plurality of data read out from said memory array are output serially through said first and second data holding means.

Claim 12

A semiconductor memory comprising: a memory array including a plurality of memory cells for storing data; an output means for outputting data read out form said memory array, said data being constituted by a plurality of bits which are read out in parallel, and said output means being provided in correspondence with each of the bits constituting said data and having a function to output a plurality of data serially read out from said memory array, wherein said output means has first data holding means for receiving data read out from said memory array through a first switching circuit, and second data holding means for receiving data read out from said memory array, the output of said second data holding means being transmitted to said first data holding means through a second switching circuit, wherein, in a random-access output operation, said first switching circuit is closed, while said second switching circuits is opened, whereby said read data is output through said first data holding means, and wherein, in a serial output operation, said first switching circuit is opened, while said second switching circuit is opened and closed at a predetermined timing, whereby said plurality of read data are output serially through said first and second data holding means; and a plurality of external terminals each provided in correspondence with said output circuit, said terminals being employed to, at least, output said data.

Claim 13

A semiconductor memory comprising: a memory array including a plurality of memory cells for storing data; an output means for outputting data read out form said memory array, said data being constituted by a plurality of bits which are read out in parallel, and said output means being provided in correspondence with each of the bits constituting said data and having a function to output a plurality of data serially read out from said memory array, wherein said output means has first data holding means for receiving data read out from said memory array through a first switching circuit, and second data holding means for receiving data read out from said memory array, the output of said second data holding means being transmitted to said first data holding means through a second switching circuit, wherein, in a random-access output operation, said first switching circuit is closed, while said second switching circuits is opened, whereby said read data is output through said first data holding means, and wherein, in a serial output operation, said first switching circuit is opened, while said second switching circuit is opened and closed at a predetermined timing, whereby said plurality of read data are output serially through said first and second data holding means; and a plurality of external terminals each provided in correspondence with said output circuit, said terminals being employed to, at least, output said data.