US4815040A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Static memory using a MIS field effect transistor
Assignee: Toshiba Corp
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Filing: 1987-09-24
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Granted: 1989-03-21
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Expires: 2007-09-24
Abstract
Abstract In a selected column, a pull-up transistor pair is not selected but, instead, a transmission gate transistor pair is selected. In the read mode, the transmission gate transistor pair serves as pull-up loads between the bit line pair. However, the transmission gate transistor pair is kept off until the voltage across the bit line pair is decreased from the power supply potential level to the threshold voltage level of the transmission gate transistors. Therefore, no DC current path is formed in the bit line pair when the voltage across the bit line pair is within a range from a voltage equal to the power supply potential level to a potential lower than the power supply potential by an amount equal to the threshold voltage level, and the rate of increase of a potential difference across the bit line pair is determined by a pull-in current of the memory cell. Therefore, a high-speed sense operation can be realized. In the write mode, the transmission gate transistor pair serves a bit line pull-up function. Since no normally-ON bit line load transistor is arranged, no direct current path including the bit line pair is present, and hence, low power consumption can be achieved.
Inventors
- 👤 Masataka Matsui
- 👤 Takayuki Ohtani
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 08:23
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/41; G11C11/413; G11C11/417; G11C11/419
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
135 words
A static memory comprising: a memory cell provided to a pair of bit lines of each column in a memory cell array; a bit line precharge circuit arranged between said pair of bit lines and a power supply terminal and driven by a bit line precharge signal; a pair of column selection transistors arranged between said pair of bit lines and a sense amplifier and controlled to be selected by an inverted column selection signal; a pair of transmission gate transistors arranged between said pair of bit lines and a pair of write data lines and controlled to be selected by a column selection signal; and a pair of bit line pull-up transistors arranged between said pair of bit lines and said power supply terminal and controlled to be nonselected by the column selection signal.
Claim 2
Dependent Claim
135 words
A static memory comprising: a memory cell provided to a pair of bit lines of each column in a memory cell array; a bit line precharge circuit arranged between said pair of bit lines and a power supply terminal and driven by a bit line precharge signal; a pair of column selection transistors arranged between said pair of bit lines and a sense amplifier and controlled to be selected by an inverted column selection signal; a pair of transmission gate transistors arranged between said pair of bit lines and a pair of write data lines and controlled to be selected by a column selection signal; and a pair of bit line pull-up transistors arranged between said pair of bit lines and said power supply terminal and controlled to be nonselected by the column selection signal.
Claim 3
Dependent Claim
121 words
A memory according to claim 1, wherein said memory cell comprises a pair of drive transistors constituting a flip-flop circuit, a load resistor connected to one of said pair of drive transistors and said power supply terminal, another load resistor connected to the other one of said pair of drive transistors and said power supply terminal, a transmission gate transistor connected to one of said pair of drive transistors and one of said pair of bit lines and having a gate connected to a word line, and another transmission gate transistor connected to the other one of said pair of drive transistors and the other one of said pair of bit lines and having a gate connected to said word line.
Claim 4
Dependent Claim
98 words
A memory according to claim 1, wherein said precharge circuit comprises an equalize transistor connected between said pair of bit lines, a pull-up transistor connected to said power supply terminal and one of said pair of bit lines, having a gate connected to the gate of said equalize transistor, and controlled to be selected by the precharge signal, and another pull-up transistor connected to said power supply terminal and the other one of said pair of bit lines, having a gate connected to the gate of said equalize transistor, and controlled to be selected by the precharge signal.
Claim 5
Dependent Claim
91 words
A memory according to claim 1, wherein said pair of column selection transistors comprise a column selection transistor connected to one input terminal of a differential sense amplifier and one of common data lines through one of said pair of bit lines and controlled to be selected by the inverted column selection signal, and another column selection transistor connected to the other one of said pair of bit lines and the other one of said pair of common data lines and controlled to be selected by the inverted column selection signal.
Claim 6
Dependent Claim
83 words
A memory according to claim 1, wherein said pair of transmission gate transistors comprise a transmission gate transistor connected between one of said pair of bit lines and one of said pair of data write lines and controlled to be selected by the column selection signal, and another transmission gate transistor connected between the other one of said pair of bit lines and the other one of said pair of data write lines and controlled to be selected by the column selection signal.
Claim 7
Dependent Claim
76 words
A memory according to claim 1, wherein said pair of bit line pull-up transistors comprise a bit line pull-up transistor connected between one of said pair of bit lines and said power supply terminal and controlled to be nonselected by the column selection signal, and another bit line pull-up transistor connected between the other one of said pair of bit lines and said power supply terminal and controlled to be nonselected by the column selection signal.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-03-20 | 1992-09-19 | 1993-03-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-03-20 | 1996-09-19 | 1997-03-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-03-20 | 2000-09-19 | 2001-03-21 | $7700.00 | Window Closed / Lapsed |