US4818982A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Brightness control for an electro-luminescent display
Assignee: Systems Management American Corp
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Filing: 1987-08-12
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Granted: 1989-04-04
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Expires: 2007-08-12
Abstract
Abstract A brightness control circuit for use with Plasma and Electroluminescent displays. The circuit receives from a computer, or other driving device, video data to be displayed, an intensity signal indicating the intensity with which to display data, a video clock and horizontal and vertical sync signals. The circuit generates first and second video fields, each having some data removed from the fields defined by the input video signal. These fields are combined to form frame data which is then modulated by the intensity signal. The result is modified video data for coupling to the display which can cause the display to display data at a low intensity.
Inventors
- 👤 Gary Kuehn
- 👤 David M. Gerrek
- 👤 Wendy Ferguson
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 10:50
CPC Classifications
G; G09; G09G; G09G3/00; G09G3/20; G09G3/2007; G09G3/2018; G09G3/2022; G09G3/2025; G09G3/22; G09G3/28; G09G3/288; G09G3/296; G09G3/30
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
220 words
A brightness control circuit for use with Plasma and Electroluminescent displays, comprising: means for receiving from a data source an input video data signal including video data to be displayed on a display, an input horizontal sync pulse signal for horizontally synchronizing said display, an input vertical sync signal for vertically synchronizing said display, an input video clock for establishing a reference for the video data, and an input intensity signal for indicating whether particular video data is to be displayed at a low or a high intensity by said display; means, coupled to said receiving means, for generating first and second video data fields each of which includes less data than its respective field component in said video data signal; means for combining said first and second video data fields to form frame data; means, coupled to said combining means, for receiving said video data and said frame data and for providing half intensity data; and means for modulating said half intensity video data with said intensity signal to provide modified video data for selectively driving said display at full intensity when said intensity signal indicates that particular video data is to be displayed at a high intensity and at half intensity when said intensity signal indicates that particular video data is to be displayed at a low intensity.
Claim 2
Dependent Claim
220 words
A brightness control circuit for use with Plasma and Electroluminescent displays, comprising: means for receiving from a data source an input video data signal including video data to be displayed on a display, an input horizontal sync pulse signal for horizontally synchronizing said display, an input vertical sync signal for vertically synchronizing said display, an input video clock for establishing a reference for the video data, and an input intensity signal for indicating whether particular video data is to be displayed at a low or a high intensity by said display; means, coupled to said receiving means, for generating first and second video data fields each of which includes less data than its respective field component in said video data signal; means for combining said first and second video data fields to form frame data; means, coupled to said combining means, for receiving said video data and said frame data and for providing half intensity data; and means for modulating said half intensity video data with said intensity signal to provide modified video data for selectively driving said display at full intensity when said intensity signal indicates that particular video data is to be displayed at a high intensity and at half intensity when said intensity signal indicates that particular video data is to be displayed at a low intensity.
Claim 3
Dependent Claim
77 words
A circuit according to claim 1 wherein said means for generating first and second video data fields comprises: means for generating intermediate vertical sync signals having twice the period of said input vertical sync signal; means for generating intermediate horizontal sync signals having twice the period of said input horizontal sync signal; means for receiving said video data and said intermediate horizontal and vertical sync signals and providing in response thereto, said first and second video fields.
Claim 4
Dependent Claim
168 words
A circuit according to claim 1 wherein said generating means comprises: a first flip-flop circuit clocked by said horizontal sync signal, having a Q output and a Q output coupled to a D input thereof; a second flip-flop circuit clocked by said vertical sync signal, having a Q output and a Q output coupled to a D input thereof; a first three input NAND gate having a first input coupled to said Q output of said first flip-flop, a second input coupled to said Q output of said second flip-flop and a third input coupled to receive said video data signal, said first NAND gate providing, at its output, said second video field; and a second three input NAND gate having a first input coupled to said Q output of said first flip-flop, a second input coupled to said Q output of said second flip-flop and a third input coupled to receive said video data signal, said second NAND gate providing, at its output, said first video field.
Claim 5
Dependent Claim
55 words
A circuit according to claim 3 wherein said combining means comprises a three input NAND gate having a first input coupled to said first NAND gate output, a second input coupled to said second NAND gate output and a third input coupled to said horizontal sync signal for providing said frame data at its output.
Claim 6
Dependent Claim
45 words
A circuit according to claim 4 wherein said means for providing half intensity data comprises a two input AND gate having a first input coupled to said video data signal and a second input coupled to receive said frame data from said third NAND gate.
Claim 7
Dependent Claim
51 words
A circuit according to claim 5 wherein said modulating means comprises a two input OR gate having a first input coupled to said half intensity data and a second input coupled to said intensity signal, said OR gate providing, at its output, said modified video data for coupling to said display.
Claim 8
Dependent Claim
23 words
A circuit according to claim 6 further including an amplifier for amplifying said modified video data before it is coupled to said display.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-04-03 | 1992-10-03 | 1993-04-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-04-03 | 1996-10-03 | 1997-04-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-04-03 | 2000-10-03 | 2001-04-04 | $7700.00 | Window Closed / Lapsed |