US4823278A
Expired / Lapsed
US
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Method of logic design of integrated circuit
Assignee: Fujitsu Ltd
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Filing: 1988-02-08
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Granted: 1989-04-18
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Expires: 2008-02-08
Abstract
Abstract A method for logic design of an integrated circuit IC in which at least one parameter concerning wiring line capacitances is used. The parameter can be precisely estimated even at a logic design stage preceding a layout design stage. The estimation is carried out by, first, classifying the logic units or the logic gates of the IC into hierarchal functional blocks. Second, specifying, for each closed network defined by delay paths, a higher level functional block in which the closed network is contained. Third, specifying lower level functional blocks enclosed by the higher functional block. Fourth, calculating the estimated wiring line capacitances of the closed network in accordance with predetermined data concerning both fan-out and actual wiring line capacitances. The data, used for the estimation, are varied in accordance with the degrees of the hierarchal level.
Inventors
- 👤 Hideo Kikuchi
- 👤 Sadao Tsutsumi
- 👤 Akira Kaneko
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 01:43
CPC Classifications
H; H10; H10D; H10D89/00; H10D89/10; G; G06; G06F; G06F30/00; G06F30/30; G06F30/32; G06F30/327; G06F30/39
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
163 words
A method for constructing an integrated circuit including designing the integrated circuit with consideration of a propagation delay time of each wiring line capacitance on a single integrated circuit chip, said method comprising the steps of: (i) classifying logic units and logic gates of the integrated circuit into hierarchal functional blocks; (ii) specifying an uppermost level functional block for a closed network and further specifying lower level functional blocks contained in the uppermost level functional block and inter-connected by the closed network; (iii) calculating estimates for wiring line capacitances in each of the functional blocks in accordance with predetermined data concerning average wiring line capacitances for every level; (iv) estimating a network wiring line capacitance of the closed network by summing the estimates for the wiring line capacitances; and (v) allocating the hierarchal functional blocks on the integrated circuit chip to form the integrated circuit, said allocating starting with the lowest level functional blocks and progressing sequentially to the uppermost level functional block.
Claim 2
Independent Claim
163 words
A method for constructing an integrated circuit including designing the integrated circuit with consideration of a propagation delay time of each wiring line capacitance on a single integrated circuit chip, said method comprising the steps of: (i) classifying logic units and logic gates of the integrated circuit into hierarchal functional blocks; (ii) specifying an uppermost level functional block for a closed network and further specifying lower level functional blocks contained in the uppermost level functional block and inter-connected by the closed network; (iii) calculating estimates for wiring line capacitances in each of the functional blocks in accordance with predetermined data concerning average wiring line capacitances for every level; (iv) estimating a network wiring line capacitance of the closed network by summing the estimates for the wiring line capacitances; and (v) allocating the hierarchal functional blocks on the integrated circuit chip to form the integrated circuit, said allocating starting with the lowest level functional blocks and progressing sequentially to the uppermost level functional block.
Claim 3
Dependent Claim
37 words
A method as set forth in claim 1, wherein, said classifying in step (i) is performed with a restriction that each of the uppermost and lower level functional blocks is provided with a single incoming delay path.
Claim 4
Dependent Claim
31 words
A method as set forth in claim 2, wherein the predetermined data in step (iii) is defined by level and fan-out of internal wiring lines existing in an average functional block.
Claim 5
Dependent Claim
18 words
A method as set forth in claim 3, wherein the level is determined by an equivalent gate number.
Claim 6
Dependent Claim
47 words
A method as set forth in claim 4, wherein the fan-out is determined by an expression X+Y-1, where X represents a number of lower level functional blocks within the average functional block, and Y represents a number of independent logic units contained in the average functional block.
Claim 7
Dependent Claim
67 words
A method as set forth in claim 5, wherein the predetermined data are provided in the form of a main table for the uppermost level functional block and a sub table for the lower level functional blocks, the main and sub tables prepared through statistical treatment of actual data measured from many different usual integrated circuits of a type similar to the integrated circuit to be designed.
Claim 8
Dependent Claim
28 words
A method as set forth in claim 6, wherein each of the main and sub tables has a plurality of rows and columns representing levels and fan-out, respectively.
Claim 9
Dependent Claim
44 words
A method as set forth in claim 7, wherein step (iii) comprises obtaining desired data from the main and sub tables, at a cross point of one of the rows and one of the columns for the level and the fan-out which are specified.
Claim 10
Dependent Claim
57 words
A method as set forth in claim 7, wherein step (iii) comprises obtaining each of the estimates for the wiring line capacitances from a corresponding cross-point in one of the main and sub tables, and wherein step (iv) comprises summing the estimates for the wiring line capacitances to determine the wiring line capacitances of the closed network.
Claim 11
Dependent Claim
153 words
A method as set forth in claim 5, wherein the predetermined data are provided in the form of a main table for the uppermost level functional block, while data corresponding to the lower level functional blocks are obtained by use of a compensation factor greater than zero and less than one, wherein step (iii) comprises the steps of: (iiiA) obtaining a main wiring line capacitance for the uppermost level functional block using the main table; and (iiiB) multiplying the compensation factor times a differental fan-out to produce an incremental wiring line capacitance due to the lower level functional blocks, where the differential fan-out is determined by a difference between the fan-out corresponding to the uppermost level functional block and a fan-out value increased by a number of lower level functional blocks in the uppermost level functional block, and wherein step (iv) comprises adding the incremental wiring line to the main wiring line capacitance.
Claim 12
Dependent Claim
109 words
A method as set forth in claim 6, wherein step (iii) comprises modifying the predetermined data obtained for the average functional block by using a variable coefficient k, the coefficient k varying in proportion to the equivalent gate number, whereby each wiring line capacitance c for a corresponding functional block is determined by the equation: c=k×c, where ##EQU5## N G denotes a value of a center number, corresponding to the average functional block, in a range of equivalent gate numbers which include the equivalent gate number N G specifying the level of the corresponding functional block, and c denotes the wiring line capacitance corresponding to the average functional block.
Claim 13
Dependent Claim
109 words
A method as set forth in claim 10, wherein step (iii) comprises modifying the predetermined data obtained for the average functional block by using a variable coefficient k, the coefficient k varying in proportion to the equivalent gate number, whereby each wiring line capacitance c for a corresponding functional block is determined by the equation: c=k×c, where ##EQU6## N G denotes a value of a center number, corresponding to the average functional block, in a range of equivalent gate numbers which include the equivalent gate number N G specifying the level of the corresponding functional block, and c denotes the wiring line capacitance corresponding to the average functional block.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-04-17 | 1992-10-17 | 1993-04-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-04-17 | 1996-10-17 | 1997-04-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-04-17 | 2000-10-17 | 2001-04-18 | $7700.00 | Window Closed / Lapsed |