US4825271A
Expired / Lapsed
US
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Nonvolatile semiconductor memory
Assignee: Toshiba Corp
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Filing: 1987-05-15
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Granted: 1989-04-25
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Expires: 2007-05-15
Abstract
Abstract Disclosed is a nonvolatile semiconductor memory having a high access speed and high reliability. The memory includes a source diffusion region extending in one direction, a pair of first word lines arranged in parallel with the source diffusion region, such that the source diffusion region is interposed therebetween, drain diffusion regions disposed to face the source diffusion region, with the first word lines interposed therebetween, bit lines electrically connected to the drain diffusion regions and arranged to cross the first word lines, a channel region formed below each of the first word lines and positioned between the source diffusion region and the drain diffusion region, a floating gate electrode formed in an electrically floating manner above the channel region and below one of the pair of the first word lines, and a second word line formed above the source region and positioned between and electrically connected to the pair of first word lines.
Inventors
- 👤 Sumio Tanaka
- 👤 Masaki Sato
- 👤 Shinji Saito
- 👤 Shigeru Atsumi
- 👤 Nobuaki Ohtsuka
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 18:23
CPC Classifications
H; H10; H10B; H10B69/00; H10B41/00; H10B41/30; Y; Y10; Y10S; Y10S257/00; Y10S257/915
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
174 words
A nonvolatile semiconductor memory, said memory including a plurality of memory cell transistors each having a source, a drain, and a floating gate which is located over a channel region formed between said source and said drain, wherein said memory also comprises: a source diffusion region extending in one direction, said source diffusion region being common to said sources of said memory cell transistors and serving as wiring of said sources; a pair of first word lines arranged in parallel with said source diffusion region, said source diffusion region being located under an area between said pair of first word lines and said pair of first word lines being located over said respective floating gates of said memory cell transistors; bit lines electrically connected to said respective drains of said memory cell transistors, said bit lines being arranged to cross said pair of first word lines; and a second word line located over the area between said pair of first word lines and electrically connected in parallel to said pair of first word lines.
Claim 2
Dependent Claim
174 words
A nonvolatile semiconductor memory, said memory including a plurality of memory cell transistors each having a source, a drain, and a floating gate which is located over a channel region formed between said source and said drain, wherein said memory also comprises: a source diffusion region extending in one direction, said source diffusion region being common to said sources of said memory cell transistors and serving as wiring of said sources; a pair of first word lines arranged in parallel with said source diffusion region, said source diffusion region being located under an area between said pair of first word lines and said pair of first word lines being located over said respective floating gates of said memory cell transistors; bit lines electrically connected to said respective drains of said memory cell transistors, said bit lines being arranged to cross said pair of first word lines; and a second word line located over the area between said pair of first word lines and electrically connected in parallel to said pair of first word lines.
Claim 3
Dependent Claim
34 words
The memory according to claim 1, which further comprises a plurality of pairs of said first word lines, wherein a second word line is provided for each of said pairs of first word lines.
Claim 4
Dependent Claim
48 words
The memory according to claim 1, wherein said plurality of memory cells are arranged along said second word line, and parts of said first word lines acting as control gates are brought into contact, via contact holes, with said second word line at intervals of several memory cells.
Claim 5
Dependent Claim
35 words
The memory according to claim 3, wherein said contact holes are formed at locations directly above said first word lines, said locations being away from the said floating gate electrodes of said memory cell transistors.
Claim 6
Dependent Claim
36 words
The memory according to claim 1, wherein said second word line has a double layer structure comprising a polysilicon layer and another layer being formed of a silicide of a metal having a high melting point.
Claim 7
Dependent Claim
66 words
The memory according to claim 5, which further comprises a first insulating layer interposed between said floating gate electrodes and said channel regions of said memory cell transistors, a second insulating layer interposed between said pair of first word lines and said floating gate electrodes of said memory cell transistors, and a field insulation layer interposed between said second word line and said first word lines.
Claim 8
Dependent Claim
20 words
The memory according to claim 6, wherein a part of said polysilicon layer extends downward into said field insulating layer.
Claim 9
Dependent Claim
15 words
The memory according to claim 1, wherein said second word line comprises a polysilicon layer.
Claim 10
Dependent Claim
79 words
The memory according to claim 8, which further comprises a first insulating layer interposed between said floating gate electrodes and said channel regions of said memory cell transistors, a second insulating layer interposed between said pair of first word lines and said floating gate electrodes of said memory cell transistors, a field insulation layer interposed between said second word line and said first word lines, wherein a part of said polysilicon layer extends downward into said field insulating layer.
Claim 11
Dependent Claim
16 words
The memory according to claim 1, wherein said second word line comprises a metal silicide layer.
Claim 12
Dependent Claim
178 words
A nonvolatile semiconductor memory which utilizes ultraviolet light for data erasure, said memory including a large number of memory cell transistors each having a source, a drain, and a floating gate which is located over a channel region formed between said source and said drain, wherein said memory also comprises: a source wiring diffusion layer, said source wiring diffusion layer being common to said sources of said memory cell transistors and serving as wiring of said sources; a pair of word lines extending in said first direction in parallel with said source wiring diffusion layer, said source wiring diffusion layer being located under an area between said pair of word lines and said pair of word lines being located over said respective floating gates of said memory cell transistors; bit lines electrically connected to said respective drains of said memory cell transistors, said bit lines extending to cross said pair of word lines; and a signal wiring located over the area between said pair of word lines and electrically connected in parallel to said pair of word lines.
Claim 13
Dependent Claim
178 words
A nonvolatile semiconductor memory which utilizes ultraviolet light for data erasure, said memory including a large number of memory cell transistors each having a source, a drain, and a floating gate which is located over a channel region formed between said source and said drain, wherein said memory also comprises: a source wiring diffusion layer, said source wiring diffusion layer being common to said sources of said memory cell transistors and serving as wiring of said sources; a pair of word lines extending in said first direction in parallel with said source wiring diffusion layer, said source wiring diffusion layer being located under an area between said pair of word lines and said pair of word lines being located over said respective floating gates of said memory cell transistors; bit lines electrically connected to said respective drains of said memory cell transistors, said bit lines extending to cross said pair of word lines; and a signal wiring located over the area between said pair of word lines and electrically connected in parallel to said pair of word lines.
Claim 14
Dependent Claim
28 words
The memory according to claim 11, which further comprises a via contact portion at which said signal wiring is brought into contact with said pair of word lines.
Claim 15
Dependent Claim
27 words
The memory according to claim 12, wherein said via contact portions are provided at a prescribed interval in said first direction of said pair of word lines.
Claim 16
Dependent Claim
13 words
The memory according to claim 11, wherein said signal wiring contains a metal.
Claim 17
Dependent Claim
13 words
The memory according to claim 11, wherein said signal wiring contains a polysilicon.
Claim 18
Dependent Claim
19 words
The memory according to claim 11, wherein said signal wiring contains a silicide of molybdenum, titanium, tungsten, or tantalum.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-04-24 | 1992-10-24 | 1993-04-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-04-24 | 1996-10-24 | 1997-04-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-04-24 | 2000-10-24 | 2001-04-25 | $7700.00 | Window Closed / Lapsed |