I/O controller for multiple disparate serial memories with a cache

Claim 1

An I/O controller for a computer system having a processor and a plurality of serial memory devices connected thereto, at least some of said memory devices differing in the rate at which data is transferred to and from said devices, comprising: a device bus; a plurality of interface means for transferring data from respective ones of said memory devices to said device bus, each of said interface means having a first input/output port connected to an input/output port of its respective one of said memory devices and a parallel second input/output port connected to said device bus, said first input/output port of at least one of said interface means being a single-bit serial port and said first input/output port of another one of said interface means being a multi-bit parallel port, all of said second input/output ports of said interface means being multi-bit parallel ports of the same width; a first-in, first-out buffer memory having an input/output port connected to said device bus for storing records of data to be stored by or read from any of said memory devices, said buffer memory having a capacity sufficient for storing a complete record of data corresponding to a single complete read or write operation to or from any of said memory devices; a buffer register having a first input/output port connected to said device bus for transferring data between said buffer register and said device bus; first control means for controlling flow of data on said device bus between said interface means and said buffer memory and between said buffer memory and said buffer register; a cache bus connected to a second input/output port of said buffer register; a cache memory for storing data received via said buffer register and said cache bus from each of said memory devices, said cache memory having an input/output port connected to said cache bus; a channel register having an input/output port connected to said cache bus and being in data communication with said processor; and second control means for controlling flow of data between said buffer register and said cache memory and between said cache memory and said channel register independently of said flow of data on said device bus between said interface means and between said buffer memory and said buffer register, whereby said buffer register serves as an interface between said device bus and said cache bus, which is separate and independently controlled relative to said device bus, and said channel register operates as an interface between said cache bus and said processor.