US4826782A
Expired / Lapsed
US
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Method of fabricating aLDD field-effect transistor
Assignee: Tektronix Inc
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Filing: 1987-04-17
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Granted: 1989-05-02
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Expires: 2007-04-17
Abstract
Abstract An intermediate structure in the fabrication of a metal-oxide semiconductor field-effect transistor is made from a substrate of p+ silicon having an elongate insulated gate structure on its main face. First and second areas of the main face are exposed along first and second opposite sides respectively of the gate structure. Donor impurity atoms are introduced into the substrate by way of at least the first area of the main face, to achieve a predetermined concentration of electrons in a region of the substrate that is subjacent the first area of the main face. The gate structure is opague to the impurity atoms. A sidewall of silicon dioxide is formed along the first side of the gate structure, whereby a strip of the first area of the main face is covered by the sidewall and other parts of the first area remain exposed adjacent the sidewall. Donor impurity atoms to which the gate structure and the sidewall are opaque are introduced into the substrate by way of the portion of the first area that is exposed adjacent the sidewall. A layer of polysilicon is disposite over the portion of the first area of the main face that is exposed adjacent the sidewall. This layer extends up the sidewall and over the gate structure. A layer of a polymer material is formed over the layer of polysilicon to a substantially uniform height over the main face. The height of the free surface of the layer of polymer material is at least as great as the maximum height of the layer of polysilicon over the gate structure. The polysilicon at a height that is at least as great as that of the gate structure is then removed.
Inventors
- 👤 Jack Sachitano
- 👤 Paul K. Boyer
- 👤 Hee K. Park
- 👤 Gregory C. Eiden
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 01:05
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/0223; H10D30/0227; H10D30/60; H10D62/00; H10D62/80; H10D62/83; H10D64/00; H10D64/01; H10D64/011; H10D64/0111; H10D64/0113; H10D64/20; H10D64/23; H10D64/251; H10D64/258; H10D64/259; H10D64/60; H10D64/62; H10P; H10P32/00; H10P32/10; H10P32/14; H10P32/1408; H10P32/1414; H10P32/17; H10P32/171; H10D62/834; Y; Y10; Y10S; Y10S148/00; Y10S148/03
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
349 words
A method of fabricating a metal-oxide-semiconductor field-effect transistor having a lightly-doped drain extension, comprising the following steps: (a) providing a substrate of semiconductor material having charge carriers of a first polarity, the substrate having a main face and an elongate insulated gate structure on its main face, and first and second areas of the main face being exposed along first and second opposite sides respectively of the gate structure, (b) introducing impurity atoms that provide charge carriers of a second polarity, opposite said first polarity, into the substrate by way of said first area of the main face, the gate structure being effective to mask the region of the substrate that is immediately subjacent the gate structure from the impurity atoms, thereby forming a first doped zone which extends partly under the gate structure and is doped to a low impurity concentration, (c) forming a sidewall of a masking material that is opaque to atoms of a selected impurity along at least said first side of the gate structure, whereby a strip of the main face along said first side of the gate structure is covered by the sidewall but other parts of the first area of the main face remain exposed, the atoms of the selected impurity providing charge carriers of said second polarity, (d) forming a layer of conductive material over said portion of said first area, over said second area, and over the gate structure, the layer of conductive material being doped with atoms of the selected impurity, PG,16 (e) heating the layer of conductive material and the substrate, whereby atoms of the selected impurity diffuse from the layer of conductive material into the substrate and impurity atoms diffuse within the substrate, thereby forming a second doped zone of a higher impurity concentration than said first doped zone, and (f) removing the conductive material of said layr that is at a height over the main face that is at least as great as that of the gate structure so as to form two discrete contacts overlying said first and second areas respectively of the main face.
Claim 2
Independent Claim
349 words
A method of fabricating a metal-oxide-semiconductor field-effect transistor having a lightly-doped drain extension, comprising the following steps: (a) providing a substrate of semiconductor material having charge carriers of a first polarity, the substrate having a main face and an elongate insulated gate structure on its main face, and first and second areas of the main face being exposed along first and second opposite sides respectively of the gate structure, (b) introducing impurity atoms that provide charge carriers of a second polarity, opposite said first polarity, into the substrate by way of said first area of the main face, the gate structure being effective to mask the region of the substrate that is immediately subjacent the gate structure from the impurity atoms, thereby forming a first doped zone which extends partly under the gate structure and is doped to a low impurity concentration, (c) forming a sidewall of a masking material that is opaque to atoms of a selected impurity along at least said first side of the gate structure, whereby a strip of the main face along said first side of the gate structure is covered by the sidewall but other parts of the first area of the main face remain exposed, the atoms of the selected impurity providing charge carriers of said second polarity, (d) forming a layer of conductive material over said portion of said first area, over said second area, and over the gate structure, the layer of conductive material being doped with atoms of the selected impurity, PG,16 (e) heating the layer of conductive material and the substrate, whereby atoms of the selected impurity diffuse from the layer of conductive material into the substrate and impurity atoms diffuse within the substrate, thereby forming a second doped zone of a higher impurity concentration than said first doped zone, and (f) removing the conductive material of said layr that is at a height over the main face that is at least as great as that of the gate structure so as to form two discrete contacts overlying said first and second areas respectively of the main face.
Claim 3
Dependent Claim
119 words
A method according to claim 1, wherein step (f) is accomplished by forming a layer of a selected material over the layer deposited in step (c), the layer of selected material having a free surface that is substantially parallel to the main face of the substrate, removing said selected material anisotropically, in a direction substantially perpendicular to said main face, until said layer of conductive material is exposed over the gate structure but not over said first area or said second area, and anisotropically removing said conductive material in a direction substantially perpendicular to said main face until the maximum height of said conductive material over said main face is less than the maximum height of the gate structure.
Claim 4
Dependent Claim
34 words
A method according to claim 2, wherein the step of anisotropically removing the conductive material is performed by etching, and the etchant is effective to remove the conductive material but not said selected material.
Claim 5
Dependent Claim
16 words
A method according to claim 2, comprising removing said selected material concurrently with said conductive material.
Claim 6
Dependent Claim
59 words
A method according to claim 1, wherein the sidewall is formed in step (c) by forming a layer of said masking material over said first and second areas and over the gate structure, and removing said masking material to a depth, perpendicular to said main face, that is substantially equal to the thickness of the layer of masking material.
Claim 7
Dependent Claim
57 words
A method of fabricating a metal-oxide-semiconductor field-effect transistor by a method in accordance with claim 1 and subsequently depositing a layer of dielectric material over said discrete contacts and over the gate structure, forming holes in the layer of dielectric material to expose the two discrete contacts and the gate structure, and depositing metal into said holes.
Claim 8
Dependent Claim
61 words
A method according to claim 6, wherein the first and second areas of the main face of the substrate are bounded respectively by first and second bodies of dielectric material and said two discrete contacts extend over said first and second bodies respectively, and the method comprises forming said holes at locations that lie over said first and second bodies respectively.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-05-01 | 1992-10-31 | 1993-05-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-05-01 | 1996-10-31 | 1997-05-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-05-01 | 2000-10-31 | 2001-05-02 | $7700.00 | Window Closed / Lapsed |