US4827448A — Random access memory cell with implanted capacito…

Claim 1

Independent Claim 310 words

An N-channel random access memory cell having a field-effect transistor and a capacitor, the transistor having a source-to-drain path and a gate, comprising: (a) a body of P-type silicon having a major face; (b) an N+ type region defined in said major face and functioning as one end of said source-to-drain path of the transistor; (c) a capacitor region in said major face spaced from the N+ type region and functioning as a lower plate of said capacitor, the capacitor region being ion implanted with N-type conductivity determining impurity to lower the apparent threshold voltage of said capacitor region; (d) a thin dielectric layer overlying said capacitor region; (e) a first conductive layer overlying said dielectric layer and functioning as an upper plate of the capacitor; (f) an insulating coating over said first conductive layer; (g) a transistor channel region in said major face between said N+ type region and said capacitor region, the channel region functioning as the source-to-drain path of the transistor; (h) a thin gate insulator layer overlying said channel region, (i) a second conductive layer overlying the gate insulator layer and functioning as said gate of the transistor and said second conductive layer also partly overlying the first conductive layer but insulated therefrom by said insulating coating; (j) an insulating layer overlying the second conductive layer; (k) a conductive metal layer overlying the insulating layer and contacting the second conductive layer through an aperture in the insulating layer at a contact area; (l) means for supplying logic signals to said N+ type region of at least two voltage levels, one of the levels being at about a reference potential and the other being a positive voltage compared to the reference potential; and (m) means for applying a bias voltage to the first conductive layer, the bias voltage having a magnitude of about half said positive voltage.

Claim 2

Dependent Claim 310 words

An N-channel random access memory cell having a field-effect transistor and a capacitor, the transistor having a source-to-drain path and a gate, comprising: (a) a body of P-type silicon having a major face; (b) an N+ type region defined in said major face and functioning as one end of said source-to-drain path of the transistor; (c) a capacitor region in said major face spaced from the N+ type region and functioning as a lower plate of said capacitor, the capacitor region being ion implanted with N-type conductivity determining impurity to lower the apparent threshold voltage of said capacitor region; (d) a thin dielectric layer overlying said capacitor region; (e) a first conductive layer overlying said dielectric layer and functioning as an upper plate of the capacitor; (f) an insulating coating over said first conductive layer; (g) a transistor channel region in said major face between said N+ type region and said capacitor region, the channel region functioning as the source-to-drain path of the transistor; (h) a thin gate insulator layer overlying said channel region, (i) a second conductive layer overlying the gate insulator layer and functioning as said gate of the transistor and said second conductive layer also partly overlying the first conductive layer but insulated therefrom by said insulating coating; (j) an insulating layer overlying the second conductive layer; (k) a conductive metal layer overlying the insulating layer and contacting the second conductive layer through an aperture in the insulating layer at a contact area; (l) means for supplying logic signals to said N+ type region of at least two voltage levels, one of the levels being at about a reference potential and the other being a positive voltage compared to the reference potential; and (m) means for applying a bias voltage to the first conductive layer, the bias voltage having a magnitude of about half said positive voltage.

Claim 3

Dependent Claim 16 words

A memory cell according to claim 1 wherein said capacitor region is ion implanted with phosphorus.

Claim 4

Dependent Claim 32 words

A memory device according to claim 1, wherein an MOS transistor source or drain region is defined at one edge of said channel region and connects to the ion implanted capacitor region.

Claim 5

Dependent Claim 106 words

In a memory cell of the type having a transistor at one face of a semiconductor body and a storage capacitor adjacent said transistor on said face for storing selected logic levels, the transistor having a channel region in series circuit with a semiconductor region of the capacitor, the capacitor having an upper plate above the semiconductor region, the improvement wherein said semiconductor region is ion-implanted to provide a threshold voltage substantially less than that exhibited by the channel region of the transistor, and means to apply a bias voltage of about half the value of the maximum of said logic levels to said upper plate.

Claim 6

Dependent Claim 106 words

In a memory cell of the type having a transistor at one face of a semiconductor body and a storage capacitor adjacent said transistor on said face for storing selected logic levels, the transistor having a channel region in series circuit with a semiconductor region of the capacitor, the capacitor having an upper plate above the semiconductor region, the improvement wherein said semiconductor region is ion-implanted to provide a threshold voltage substantially less than that exhibited by the channel region of the transistor, and means to apply a bias voltage of about half the value of the maximum of said logic levels to said upper plate.

Claim 7

Dependent Claim 22 words

In an MOS memory cell according to claim 4, the channel region being contiguous with said one edge of the semiconductor region.

Claim 8

Dependent Claim 44 words

In an MOS memory cell according to claim 4, a first conductive layer overlying a first thin oxide coating providing the gate of the transistor, and a second conductive layer overlying a second thin oxide coating providing the upper plate of the storage capacitor.

Claim 9

Dependent Claim 24 words

In an MOS memory cell according to claim 6, the first and second conductive layers being polycrystalline silicon and one partially overlying the other.

Claim 10

Dependent Claim 26 words

In an MOS memory cell according to claim 7 wherein the semiconductor region extends beyond the second conductive layer in the direction of the channel region.

Claim 11

Dependent Claim 207 words

A memory device comprising a plurality of memory cells, each memory cell formed at a face of a silicon body and having an insulated-gate field effect transistor and capacitance means, the transistor including a conductive gate and a source-to-drain path formed in said face, a gate insulator layer separating the conductive gate from the face, a heavily doped region at one end of the source-to-drain path in said face, the heavily doped region connected to an elongated sense line for application of logic-level voltages thereto, the capacitance means including a conductive plate and a dielectric thinner than said gate insulator insulating said conductive plate from said face, and further including a capacitor region in said face beneath said plate, said capacitor region being ion-implanted with impurity at a doping level less than that of said heavily-doped region. Said conductive plate being part of a wider conductor layer which forms the conductive plate of the capacitance means of a number of like cells along said face, said conductor strip being connected to a selected potential having a level in the range of zero to about half of said logic-level voltage, and elongated conductive means forming the gates of at least two memory cells and extending along the face.

Claim 12

Dependent Claim 207 words

A memory device comprising a plurality of memory cells, each memory cell formed at a face of a silicon body and having an insulated-gate field effect transistor and capacitance means, the transistor including a conductive gate and a source-to-drain path formed in said face, a gate insulator layer separating the conductive gate from the face, a heavily doped region at one end of the source-to-drain path in said face, the heavily doped region connected to an elongated sense line for application of logic-level voltages thereto, the capacitance means including a conductive plate and a dielectric thinner than said gate insulator insulating said conductive plate from said face, and further including a capacitor region in said face beneath said plate, said capacitor region being ion-implanted with impurity at a doping level less than that of said heavily-doped region. Said conductive plate being part of a wider conductor layer which forms the conductive plate of the capacitance means of a number of like cells along said face, said conductor strip being connected to a selected potential having a level in the range of zero to about half of said logic-level voltage, and elongated conductive means forming the gates of at least two memory cells and extending along the face.

Claim 13

Dependent Claim 88 words

A memory cell according to claim 9 wherein first and second conductive levels are included in the cell, with the second conductive level at least partially overlying the first conductive level but insulated therefrom, the first conductive level providing said conductive plate and said wider conductor layer, the second conductive level providing the conductive gate of the transistor, the other end of said source-to-drain path of the transistor being provided by an edge of said capacitor region, the elongated conductive means being defined by the second conductive level.

Claim 14

Dependent Claim 20 words

A memory cell according to claim 9, wherein the capacitor region is an implanted region having a low threshold voltage.

Claim 15

Dependent Claim 38 words

A memory cell according to claim 11, wherein the capacitor region is an inverted region and the selected potential is a voltage of substantially less than logic levels stored in the capacitance means in operation of the cell.

Claim 16

Dependent Claim 212 words

An array of memory cells formed in a face of a semiconductor body, each cell having an insulated-gate field-effect transistor and capacitance means; the transistor of each cell including a conductive gate and including a source-to-drain path formed in said face, a gate insulator layer separating the conductive gate from the face, a heavily doped region as one end of the source-to-drain path in said face, the heavily doped region connected to an elongated sense line extending along said face, and elongated conductive means coupled to the conductive gate and extending along said face; the capacitance means of each cell storing logic voltage levels of predetermined magnitude and including a semiconductor region and a conductive plate, the conductive plate being separated from said semiconductor region in said face by a dielectric thinner than said gate insulator, the semiconductor region being ion-implanted at a doping level less than that of said heavily-doped region, the conductive plate being part of a wider conductor layer which forms part of like capacitance means of a number of other ones of said memory cells along said face, said conductor layer being connected to a selected potential; wherein said selected potential is in the range of zero to substantially less than the maximum of said logic voltage levels.

Claim 17

Dependent Claim 212 words

An array of memory cells formed in a face of a semiconductor body, each cell having an insulated-gate field-effect transistor and capacitance means; the transistor of each cell including a conductive gate and including a source-to-drain path formed in said face, a gate insulator layer separating the conductive gate from the face, a heavily doped region as one end of the source-to-drain path in said face, the heavily doped region connected to an elongated sense line extending along said face, and elongated conductive means coupled to the conductive gate and extending along said face; the capacitance means of each cell storing logic voltage levels of predetermined magnitude and including a semiconductor region and a conductive plate, the conductive plate being separated from said semiconductor region in said face by a dielectric thinner than said gate insulator, the semiconductor region being ion-implanted at a doping level less than that of said heavily-doped region, the conductive plate being part of a wider conductor layer which forms part of like capacitance means of a number of other ones of said memory cells along said face, said conductor layer being connected to a selected potential; wherein said selected potential is in the range of zero to substantially less than the maximum of said logic voltage levels.

Claim 18

Dependent Claim 95 words

An array of memory cells according to claim 13 wherein first and second conductive levels are included in the array, the second conductive level at least partially overlying the first conductive level but insulated therefrom, the first conductive level providing said conductive plate and said wider conductor layer, the second conductive level providing said elongated conductive means and the gate of the transistor, the capacitance means including a capacitor region in said face beneath said plate, the other end of the source-to-drain path of the transistor being provided by an edge of the capacitor region.

Claim 19

Dependent Claim 22 words

An array of memory cells according to claim 13, wherein the capacitor region is an implanted region having a low threshold voltage.

Claim 20

Dependent Claim 143 words

A memory cell comprising: an insulated gate field effect transistor having a source to drain path at a face of a semiconductor body and a gate on said face, the gate being insulated from the source-to-drain path by a gate insulator layer, capacitor means at said face and coupled to said capacitor means having a grounded conductive plate above the face and an ion-implanted semiconductor region in said face, the conductive plate being insulated from said semiconductor region by a capacitor insulator layer, said gate insulator layer being substantially thicker than said capacitor insulator layer, said semiconductor region being coupled to said source-to-drain path; wherein said ion-implanted semiconductor region beneath said conductive plate is doped at a level less than that of one end of said source-to-drain path, and exhibits threshold voltage lower than that exhibited by said source-to-drain path beneath said gate.

Claim 21

Dependent Claim 143 words

A memory cell comprising: an insulated gate field effect transistor having a source to drain path at a face of a semiconductor body and a gate on said face, the gate being insulated from the source-to-drain path by a gate insulator layer, capacitor means at said face and coupled to said capacitor means having a grounded conductive plate above the face and an ion-implanted semiconductor region in said face, the conductive plate being insulated from said semiconductor region by a capacitor insulator layer, said gate insulator layer being substantially thicker than said capacitor insulator layer, said semiconductor region being coupled to said source-to-drain path; wherein said ion-implanted semiconductor region beneath said conductive plate is doped at a level less than that of one end of said source-to-drain path, and exhibits threshold voltage lower than that exhibited by said source-to-drain path beneath said gate.

Claim 22

Dependent Claim 25 words

A cell according to claim 16 wherein said gate insulator layer and said capacitor insulator layer are both silicon oxide, and said body is silicon.

Claim 23

Dependent Claim 17 words

A cell according to claim 17 wherein said gate and said conductive plate are both polycrystalline silicon.

Claim 24

Dependent Claim 24 words

A cell according to claim 16 wherein said semiconductor region is ion-implanted with an impurity of type opposite the predominate impurity in said body.

Claim 25

Dependent Claim 208 words

A memory device including a plurality of memory cells each having a transistor including a gate insulator and a source-to-drain path, and a capacitor having a dielectric separating first and second plates at a face of a semiconductor body comprising: a first conductor overlying said gate insulator on said face to form a gate defining said source-to-drain path of said transistor in said face; a first doped region formed at one end of said source-to-drain path, said first doped region being coupled to a sense line for providing logic signals to said one end of said source-to-drain path; a second doped region connected to a second end of said source-to-drain path; and a second conductor overlying said dielectric to form said first plate and defomimg a capacitor region in said face including at least part of said second doped region to form said second plate, said dielectric having a thickness less than that of said gate insulator, said capacitor region being doped to a level that is less than that of said capacitor region being region, said first conductor at least partially overlying said second conductor; said second conductor connected to a selected voltage having a level less than the maximum potential applied for storage on said capacitor.

Claim 26

Dependent Claim 208 words

A memory device including a plurality of memory cells each having a transistor including a gate insulator and a source-to-drain path, and a capacitor having a dielectric separating first and second plates at a face of a semiconductor body comprising: a first conductor overlying said gate insulator on said face to form a gate defining said source-to-drain path of said transistor in said face; a first doped region formed at one end of said source-to-drain path, said first doped region being coupled to a sense line for providing logic signals to said one end of said source-to-drain path; a second doped region connected to a second end of said source-to-drain path; and a second conductor overlying said dielectric to form said first plate and defomimg a capacitor region in said face including at least part of said second doped region to form said second plate, said dielectric having a thickness less than that of said gate insulator, said capacitor region being doped to a level that is less than that of said capacitor region being region, said first conductor at least partially overlying said second conductor; said second conductor connected to a selected voltage having a level less than the maximum potential applied for storage on said capacitor.

Claim 27

Dependent Claim 27 words

A memory device according to claim 20, wherein said capacitor region is an implanted region having a threshold voltage that is lower than that of said transistor.

Claim 28

Dependent Claim 31 words

A memory device according to claim 20, wherein said first doped region forms another end of a second source-to-drain path of at least one other memory cell formed at said face.

Claim 29

Dependent Claim 15 words

A memory cell according to claim 20, wherein said first and second conductors comprise polysilicon.

Claim 30

Dependent Claim 30 words

A memory device according to claim 20, wherein said first conductor defines an elongated conductor that forms the gate electrode of at least one other transistor formed at said face.

Claim 31

Dependent Claim 32 words

A memory device according to claim 20, wherein said second conductor comprises a layer extending along said face to form other plates for a number of like memory cells along said face.

Claim 32

Dependent Claim 29 words

A memory device according to claim 24, further comprising a third conductor connected to said first conductor for providing a control signal to said at least one other transistor.

Claim 33

Dependent Claim 23 words

A memory device according to claim 20, wherein said capacitor region is doped to the same doping level as said second doped region.

Claim 34

Dependent Claim 29 words

A memory device according to claim 20, wherein said first doped region forms the source of said transistor and said second doped region forms the drain of said transistor.

Claim 35

Dependent Claim 38 words

A memory device according to claim 20, wherein said capacitor region is an inverted region and said selected voltage is a voltage of less than the maximum voltage stored by said capacitor during operation of said memory cell.

Claim 36

Dependent Claim 24 words

A memory device according to claim 20, wherein said sense line comprises an elongated doped region formed in the face of said semiconductor body.

Claim 37

Dependent Claim 50 words

A memory device according to claim 20, further comprising a conductive strip coupled to said gate at a first location and coupled to at least a second gate of a second transistor at a second location, said conductive strip forming a control line for said gate and said second gate.

Claim 38

Dependent Claim 173 words

A memory device including a plurality of memory cells each having a transistor including a gate and a source-to-drain path, and a capacitor having a dielectric separating first and second plates at a face of a semiconductor body comprising: a first conductive layer forming a gate on said gate insulator overlying selected regions of said face and at least partially overlying the source-to-drain path of a first and second transistor; a doped region formed at one end of the source-to-drain path of said first and a third transistor; a second conductive layer forming said first plates over said dielectric and defining a plurality of capacitor regions in said face to form said second plates; said dielectric being thinner than said gate insulator, said capacitor regions doped to a level less than said first plurality of doped regions, and said first plates connected to a potential within the range of zero to less than the maximum potential applied for storage on said capacitors; and a third conductive layer connected to said first conductive layer.

Claim 39

Dependent Claim 173 words

A memory device including a plurality of memory cells each having a transistor including a gate and a source-to-drain path, and a capacitor having a dielectric separating first and second plates at a face of a semiconductor body comprising: a first conductive layer forming a gate on said gate insulator overlying selected regions of said face and at least partially overlying the source-to-drain path of a first and second transistor; a doped region formed at one end of the source-to-drain path of said first and a third transistor; a second conductive layer forming said first plates over said dielectric and defining a plurality of capacitor regions in said face to form said second plates; said dielectric being thinner than said gate insulator, said capacitor regions doped to a level less than said first plurality of doped regions, and said first plates connected to a potential within the range of zero to less than the maximum potential applied for storage on said capacitors; and a third conductive layer connected to said first conductive layer.

Claim 40

Dependent Claim 27 words

A memory device according to claim 32, where in said capacitor regions are implanted regions having a threshold voltage that is lower than that of said transistor.

Claim 41

Dependent Claim 20 words

A memory device according to claim 32, wherein said first conductive layer at least partially overlies said second conductive layer.

Claim 42

Dependent Claim 16 words

A memory device according to claim 32, wherein said first and second conductive layers comprise polysilicon.

Claim 43

Dependent Claim 32 words

A memory device according to claim 32, wherein said first plurality of doped regions are each connected to an elongated sense line for providing logic signals to said plurality of memory cells.

Claim 44

Dependent Claim 28 words

A memory device according to claim 32, wherein said third conductive layer forms an elongated control line to provide an activating signal to said first and second transistors.

Claim 45

Dependent Claim 21 words

A memory device according to claim 9, wherein said elongated sense line comprises an elongated doped region formed in said face.

Claim 46

Dependent Claim 31 words

A memory device according to claim 9, wherein said elongated sense line is connected to at least one other heavily doped region in a like memory cell formed at said face.

Claim 47

Dependent Claim 195 words

A memory device including a plurality of memory cells each having a transistor including a gate insulator and a source-to-drain path and a capacitor having a dielectric separating first and second plates at a face of a semiconductor body comprising: a first conductor overlying said gate insulator on said face to form a gate defining said source-to-drain path of said transistor in said face; a first doped region formed at one end of said source-to-drain path, said first doped region being coupled to a sense line for providing logic signals to said one end of said source-to-drain path; a second doped region formed at a second end of said source-to-drain path; and a second conductor overlying said dielectric to form said first plate and defining a capacitor region in said face including at least part of said second doped region to form said second plate, said dielectric having a thickness less than that of said gate insulator, said capacitor region being doped to a level that is less than that of said first doped region and said second conductor connected to a voltage having a level about half of the level of said logic signals.

Claim 48

Dependent Claim 195 words

A memory device including a plurality of memory cells each having a transistor including a gate insulator and a source-to-drain path and a capacitor having a dielectric separating first and second plates at a face of a semiconductor body comprising: a first conductor overlying said gate insulator on said face to form a gate defining said source-to-drain path of said transistor in said face; a first doped region formed at one end of said source-to-drain path, said first doped region being coupled to a sense line for providing logic signals to said one end of said source-to-drain path; a second doped region formed at a second end of said source-to-drain path; and a second conductor overlying said dielectric to form said first plate and defining a capacitor region in said face including at least part of said second doped region to form said second plate, said dielectric having a thickness less than that of said gate insulator, said capacitor region being doped to a level that is less than that of said first doped region and said second conductor connected to a voltage having a level about half of the level of said logic signals.

Claim 49

Dependent Claim 29 words

A memory device according to claim 40, wherein said capacitor region is an implanted region having a threshold voltage that is lower than that of said field effect transistor.

Claim 50

Dependent Claim 31 words

A memory device according to claim 40, wherein said first doped region forms another end of a second source-to-drain path of at least one other memory cell formed at said face.

Claim 51

Dependent Claim 15 words

A memory device according to claim 40, wherein said first and second conductors comprise polysilicon.

Claim 52

Dependent Claim 30 words

A memory device according to claim 40, wherein said first conductor defines an elongated conductor that forms the gate electrode of at least one other transistor formed at said face.

Claim 53

Dependent Claim 30 words

A memory device according to claim 40, wherein said second conductor comprises a layer extending along said face and including other conductive plates for a number of like memory cells.

Claim 54

Dependent Claim 29 words

A memory device according to claim 44, further comprising a third conductor connected to said first conductor for providing a control signal to said at least one other transistor.

Claim 55

Dependent Claim 23 words

A memory device according to claim 40, wherein said capacitor region is doped to the same doping level as said second doped region.

Claim 56

Dependent Claim 29 words

A memory device according to claim 40, wherein said first doped region forms the source of said transistor and said second doped region forms the drain of said transistor.

Claim 57

Dependent Claim 24 words

A memory device according to claim 40, wherein said sense line comprises an elongate doped region formed in the face of said semiconductor body.

Claim 58

Dependent Claim 50 words

A memory device according to claim 40, further comprising a conductive strip coupled to said gate at a first location and coupled to at least a second gate of a second transistor at a second location, said conductive strip forming a control line for said gate and said second gate.

Claim 59

Dependent Claim 18 words

A memory device according to claim 40, wherein said first conductor at least partially overlies said second conductor.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	1992-05-01	1992-10-31	1993-05-02	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	1996-05-01	1996-10-31	1997-05-02	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	2000-05-01	2000-10-31	2001-05-02	$7700.00	Window Closed / Lapsed

Random access memory cell with implanted capacitor region

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