Ferromagnetic gate memory

Claim 2

A nonvolatile memory cell comprising: a substrate of first conductivity type; a gate formed from a ferromagnetic, conductive material, said gate overlying a channel region in said substrate; first and second doped regions of a second conductivity type separated by said channel region, said channel region being conductive in either of a first or a second direction in response to a voltage differential between said first and second doped regions when a voltage is applied to said gate; and said gate assuming a first magnetic orientation in response to high current through said channel region in said first direction and a second magnetic orientation in response to a high current through said channel region in said second direction, in order to write selected data into the cell.

Claim 3

The memory cell of claim 1 and further comprising circuitry to determine the magnetic orientation of said gate region in order to read data from the cell.

Claim 4

The memory cell of claim 1 wherein low current through said channel region is deflected in a third direction in response to said first magnetic orientation and in a fourth direction in response to said second magnetic orientation.

Claim 5

The memory cell of claim 2 wherein said circuitry comprises means for determining the direction of deflection of a small current passed through said channel region.

Claim 6

The memory cell of claim 4 wherein said means for determining the direction of deflection comprises circuitry to measure the magnitude of a current generated in response to a voltage differential between said doped regions.

Claim 7

The memory cell of claim 4 wherein said circuitry for determining the direction of deflection comprises a differential current sense amplifier.

Claim 8

The memory cell of claim 1 and further comprising: means for receiving a data input having either a logical high or a logical low value; and circuitry to pass a high current from said first doped region to said second doped region in response to a logical high input and pass a high current from said second doped region to said first doped region in response to a logical low input.

Claim 9

The memory cell of claim 1 wherein the surface of said substrate below said gate is manufactured such that the mobility of electrons at said surface is impeded.

Claim 10

The memory cell of claim 1 wherein said gate comprises a layer of nickel-iron alloy.

Claim 11

The memory cell of claim 1 wherein said first conductivity type comprises a P type material and said second conductivity type comprises an N type material.

Claim 12

A nonvolatile memory array comprising: a substrate of a first conductivity type; a plurality of ferromagnetic regions overlying respective channel regions in said substrate region, said ferromagnetic regions being aligned substantially parallel to each other; a plurality of doped regions of a second conductivity type aligned substantially parallel to one and substantially normal to said ferromagnetic regions; and said ferromagnetic regions assuming a first magnetic orientation in response to a high current passed through a portion of said channels between adjacent doped regions in a first direction and assuming a second magnetic orientation in response to a high current through said portion of said channel in a second direction, said magnetic orientation being local to a portion of said ferromagnetic region above said portion of said channel region through which said high current is passed, such that selected logic data is stored in said ferromagnetic region in response to the passing of high current through said channel regions.

Claim 13

A nonvolatile memory array comprising: a substrate of a first conductivity type; a plurality of ferromagnetic regions overlying respective channel regions in said substrate region, said ferromagnetic regions being aligned substantially parallel to each other; a plurality of doped regions of a second conductivity type aligned substantially parallel to one and substantially normal to said ferromagnetic regions; and said ferromagnetic regions assuming a first magnetic orientation in response to a high current passed through a portion of said channels between adjacent doped regions in a first direction and assuming a second magnetic orientation in response to a high current through said portion of said channel in a second direction, said magnetic orientation being local to a portion of said ferromagnetic region above said portion of said channel region through which said high current is passed, such that selected logic data is stored in said ferromagnetic region in response to the passing of high current through said channel regions.

Claim 14

The memory array of claim 11 wherein a high current is passed between adjacent doped regions by applying a high voltage to ones of said doped regions and a low voltage to other ones of said doped regions.

Claim 15

The memory array of claim 11 and further comprising circuitry to generate a voltage differential between a first selected doped region and a second selected doped region in order to generate a current therebetween, said first and second selected doped regions being adjacent each other on opposite sides of one of said ferromagnetic regions.

Claim 16

The memory array of claim 11 and further comprising circuitry for determining the magnetic orientation of the predetermined portion of said ferromagnetic regoin.

Claim 17

The memory array of claim 14 wherein said circuitry for determining the magnetic orientation cmprises comparator circuitry for measuring a current generated in response to a predetermined voltage applied between doped regions defining said portion of said ferromagnetic region and comparing said measured current to a reference current.

Claim 18

The memory array of claim 15 wherein said compare circuitry comprises a differential current sense amplifier.

Claim 21

The method of claim 17 and further comprising: applying a voltage to said gate region to enable said channel region to conduct.

Claim 22

The method of claim 17 wherein said high current is generated by creating a voltage between said first and second doped regions.

Claim 23

The method of claim 17 and further including reading the data bit stored in the gate region, comprising the steps of: applying a voltage across said channel region to generate a current therethrough; detecting the magnitude of the generated current; and comparing the detected magnitude with predetermined magnitudes to determine the orientation of the magnetic field of the gate region.

Claim 26

The method of claim 21 wherein a magnetic orientation corresponding to the first logical value deflects said electrons toward the surface of the substrate below said gate region and a magnetic orientation corresponding to a second logical value deflects said electrons towards the bottom of the channel region.

Claim 27

The method of claim 22 and further comprising the step of further impeding the mobility of electrons at the surface of said substrate.

Claim 28

The method of claim 22 wherein said step of detecting the direction of deflection comprises measuring the level of current created in response to said predetermined voltage between said first and second doped regions.