US4831572A
Expired / Lapsed
US
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Polynomial vector arithmetic operation control system
Assignee: NEC Corp
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Filing: 1987-06-30
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Granted: 1989-05-16
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Expires: 2007-06-30
Abstract
Abstract A system for controlling polynomial arithmetic operations of a vector arithmetic processor capable of executing the arithmetic operations independently of a central processing unit (CPU), includes, in the vector arithmetic processor, a circuit for modifying an instruction code supplied from the CPU on the basis of a signal representing that the instruction supplied from the CPU is a vector arithmetic instruction and a signal for commanding switching of the instruction code from the CPU, and an instruction decoder addressed in response to an output from the modification circuit to output an instruction word to an arithmetic unit.
Inventors
- 👤 Sunao Sekiguchi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 22:45
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/30003; G06F9/30007; G06F9/3001; G06F15/00; G06F15/76; G06F15/80; G06F15/8053; G06F9/30145
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
109 words
A system for controlling arithmetic operation of a vector arithmetic processor capable of executing arithmetic operations independently of a CPU, comprising, in said vector arithmetic processor; an instruction code register for storing an instruction code supplied from said CPU, means for determining whether the instruction code currently stored in said instruction code register requires instruction code switching, and storing a signal representing a determination result, a register for storing an instruction code switching signal resettable from said CPU, and modification circuit means for modifying an output form said instruction code register on the basis of outputs from said determining means and said register and for outputting a modified signal.
Claim 2
Independent Claim
109 words
A system for controlling arithmetic operation of a vector arithmetic processor capable of executing arithmetic operations independently of a CPU, comprising, in said vector arithmetic processor; an instruction code register for storing an instruction code supplied from said CPU, means for determining whether the instruction code currently stored in said instruction code register requires instruction code switching, and storing a signal representing a determination result, a register for storing an instruction code switching signal resettable from said CPU, and modification circuit means for modifying an output form said instruction code register on the basis of outputs from said determining means and said register and for outputting a modified signal.
Claim 3
Dependent Claim
49 words
A system according to claim 1, wherein said instruction code modification circuit comprises means for modifying at least one bit of an n-bit instruction input from said instruction code register on the basis of the outputs from said first an second registers and for outputting a modified instruction code.
Claim 4
Independent Claim
162 words
A system for controlling arithmetic operation of a vector arithmetic processor capable of executing arithmetic operations independently of a CPU, comprising, in said vector arithmetic processor, an instruction code register for storing an instruction code supplied from said CPU, a first register for storing a signal representing whether the instruction code currently stored in said instruction code register requires switching, a second register for storing an instruction code switching signal resettable from said CPU, modification circuit means for modifying an output from said instruction code register on the basis of outputs from said first and second registers and for outputting a modified signal, an instruction decoder addressed in response to an output from said instruction code modification circuit means to output an instruction word, some bits of the instruction word being supplied to said first register, as the signal to be stored therein and means for executing an arithmetic operation on the basis of the instruction code output from said instruction decoder.
Claim 5
Independent Claim
162 words
A system for controlling arithmetic operation of a vector arithmetic processor capable of executing arithmetic operations independently of a CPU, comprising, in said vector arithmetic processor, an instruction code register for storing an instruction code supplied from said CPU, a first register for storing a signal representing whether the instruction code currently stored in said instruction code register requires switching, a second register for storing an instruction code switching signal resettable from said CPU, modification circuit means for modifying an output from said instruction code register on the basis of outputs from said first and second registers and for outputting a modified signal, an instruction decoder addressed in response to an output from said instruction code modification circuit means to output an instruction word, some bits of the instruction word being supplied to said first register, as the signal to be stored therein and means for executing an arithmetic operation on the basis of the instruction code output from said instruction decoder.
Claim 6
Independent Claim
174 words
A system for controlling arithmetic operation of a vector arithmetic processor capable of executing arithmetic operations independently of a CPU, comprising, in said vector arithmetic processor; an instruction code register for storing an instruction code supplied from said CPU, register means for inputting a first signal representing that the instruction currently stored in the instruction code register is a polynomial vector arithmetic instruction and a second signal for commanding initiation of arithmetic operation of said vector arithmetic processor from said CPU to generate a third signal based on the first signal and the second signal, instruction code modification circuit means for modifying an output from said instruction code register on the basis of the third signal, an instruction decoder addressed in response to an output from said instruction code modification circuit means to output the instruction code and to supply some bits of the instruction word as the first signal to said register means, and arithmetic means for executing an arithmetic operation on the basis of the instruction word output from said instruction decoder.
Claim 7
Independent Claim
174 words
A system for controlling arithmetic operation of a vector arithmetic processor capable of executing arithmetic operations independently of a CPU, comprising, in said vector arithmetic processor; an instruction code register for storing an instruction code supplied from said CPU, register means for inputting a first signal representing that the instruction currently stored in the instruction code register is a polynomial vector arithmetic instruction and a second signal for commanding initiation of arithmetic operation of said vector arithmetic processor from said CPU to generate a third signal based on the first signal and the second signal, instruction code modification circuit means for modifying an output from said instruction code register on the basis of the third signal, an instruction decoder addressed in response to an output from said instruction code modification circuit means to output the instruction code and to supply some bits of the instruction word as the first signal to said register means, and arithmetic means for executing an arithmetic operation on the basis of the instruction word output from said instruction decoder.
Claim 8
Independent Claim
151 words
A system for controlling arithmetic operation of a vector arithmetic processor capable of executing arithmetic operations independently of a CPU, comprising, in said vector arithmetic processor, an instruction code register for storing an instruction code supplied from said CPU, register means for receiving an arithmetic operation start signal supplied from said CPU to said vector arithmetic processor, the arithmetic operation start signal including a signal representing that the instruction stored in said instruction code register is a polynomial vector arithmetic instruction, and for outputting a signal, instruction code modification circuit means for modifying an output from said instruction code register in response to the signal output from said register means, an instruction decoder addressed in response to an output from said instruction code modification circuit means to output an instruction word, and arithmetic means for executing an arithmetic operation on the basis of the instruction word output from said instruction decoder.
Claim 9
Independent Claim
151 words
A system for controlling arithmetic operation of a vector arithmetic processor capable of executing arithmetic operations independently of a CPU, comprising, in said vector arithmetic processor, an instruction code register for storing an instruction code supplied from said CPU, register means for receiving an arithmetic operation start signal supplied from said CPU to said vector arithmetic processor, the arithmetic operation start signal including a signal representing that the instruction stored in said instruction code register is a polynomial vector arithmetic instruction, and for outputting a signal, instruction code modification circuit means for modifying an output from said instruction code register in response to the signal output from said register means, an instruction decoder addressed in response to an output from said instruction code modification circuit means to output an instruction word, and arithmetic means for executing an arithmetic operation on the basis of the instruction word output from said instruction decoder.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-05-15 | 1992-11-14 | 1993-05-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-05-15 | 1996-11-14 | 1997-05-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-05-15 | 2000-11-14 | 2001-05-16 | $7700.00 | Window Closed / Lapsed |