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US4837179A Expired / Lapsed US ⏱️ 0.0 years remaining

Method of making a LDD mosfet

Assignee: Plessey Semiconductors Ltd
•
Filing: 1986-10-31
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Granted: 1989-06-06
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Expires: 2006-10-31
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Abstract

Abstract A method (FIG. 3) for producing MOS transistors of the type having shallow, lightly doped, source/drain structure. In this method sidewall fillets (7) of n-type doped dielectric material are defined adjacent to the sides of the oxide (1) and metal electrode (3) features. These fillets (7) are then employed to provide self aligned masking during implantation of heavy dopant of either n- or p- type (9; 13). In a subsequent rapid anneal step, the implant dopant is activated and n-type dopant diffused into the substrate (5) from the fillets (7) to provide lightly doped source/drain structures (11; 15). Examples of this method are described for producing phosphorus-arsenic n - /n + are phosphorus-boron p - /p + source/drain structures.

Inventors

  • 👤 David J. Foster
  • 👤 Andrew J. Pickering

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-09 13:14
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/0223; H10D30/0227; H10D30/60; H10D30/601; H10D30/605; H10P; H10P32/00; H10P32/10; H10P32/14; H10P32/1408; H10P32/141; H10P32/17; H10P32/171; Y; Y10; Y10S; Y10S438/00; Y10S438/914; Y10S438/919

Claims Analysis

Total Claims: 7
Claim 1
Independent Claim 126 words
A method for MOS transistor manufacture comprising essentially the following steps: firstly, defining on a substrate of silicon crystal material a mesa comprised of a gate oxide and a gate electrode; secondly, applying to the gate oxide, gate electrode, and substrate, a deposit of dielectric material incorporating a quantity of n-type dopant, and etching same to create a narrow sidewall adjacent to both the gate oxide and the gate electrode; thirdly, introducing a heavy implant dose of p-type dopant species, to produce a shallow implant in the substrate aligned to the side of the sidewall; and, fourthly, annealing the substrate to regrow the silicon crystal, to activate the implanted dopant, and to drive incorporated dopant from the sidewall into the substrate to form a counter-doped region.
Claim 2
Independent Claim 126 words
A method for MOS transistor manufacture comprising essentially the following steps: firstly, defining on a substrate of silicon crystal material a mesa comprised of a gate oxide and a gate electrode; secondly, applying to the gate oxide, gate electrode, and substrate, a deposit of dielectric material incorporating a quantity of n-type dopant, and etching same to create a narrow sidewall adjacent to both the gate oxide and the gate electrode; thirdly, introducing a heavy implant dose of p-type dopant species, to produce a shallow implant in the substrate aligned to the side of the sidewall; and, fourthly, annealing the substrate to regrow the silicon crystal, to activate the implanted dopant, and to drive incorporated dopant from the sidewall into the substrate to form a counter-doped region.
Claim 3
Dependent Claim 21 words
A method, as claimed in claim 1, wherein the incorporated n-type dopant is phosphorus and the implant dopant species is boron.
Claim 4
Dependent Claim 35 words
A method, as claimed in claim 2, wherein the implant is introduced at an energy in the range 5 to 25 keV and at a dose of 10 15 to 10 16 /cm 2 .
Claim 5
Dependent Claim 28 words
A method, as claimed in claim 3, wherein the step of anealing is performed at a temperature of 1100°±50° C. for a period of 15 to 30 seconds.
Claim 6
Dependent Claim 13 words
A method, as claimed in claim 1, wherein the dielectric is silicon oxide.
Claim 7
Dependent Claim 25 words
A method, as claimed in claim 5, wherein the dopant is phosphorus, which dopant is incorporated in the quantity 4 to 6 percent by weight.

References Cited (Backward Citations)

US4080618A Cited
US4062699A Cited
EP0010633A1 Cited
US4209350A Cited
US4356623A Cited
US4356623B1 Cited
US4417347A Cited
EP0083785A2 Cited
US4419810A Cited
US4546535A Cited
EP0173953A2 Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1992-06-05 1992-12-05 1993-06-06 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1996-06-05 1996-12-05 1997-06-06 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2000-06-05 2000-12-05 2001-06-06 $7700.00 Window Closed / Lapsed

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