Fuse status detection circuit

Claim 2

A fuse state detection circuit for detecting the status of a fuse, the circuit comprising: first and second terminal means adapted for electrical connection to first and second voltage sources, respectively; a flip-flop circuit electrically connected between first and second terminal means comprising two fuses and further comprising two transistors each having a control region, each fuse being in a load circuit of one of the transistors with the control region of each transistor being electrically connected to the load circuit of the other transistor, each fuse providing a conductive path of a selected conductivity which is of a relatively high conductivity in the form in which the fuse is initially provided but of a relatively low conductivity if blown; and an initializing element electrically connected between a selected one of said first and second terminal means and a selected one of said transistor control region, wherein said initializing element includes a capacitor comprising a thin film metal layer which overlies and is separated from a doped semiconductor region by an insulating layer, and whereby, if the detection circuit is electrically energized, a first predetermined signal is provided if the fuses are conducting and a second predeterined signal is provided if the fuses are blown.

Claim 3

The apparatus of claim 1 wherein the fuse comprises a member of conductive polysilicon.

Claim 4

The apparatus of claim 2 wherein one of the transistors is a p channel MOS transistor and the other transistor is a n channel MOS transistor.

Claim 5

A fuse status detection circuit for detecting the status of a fuse, the circuit comprising: first and second terminal means adapted for electrical connection to first and second voltage sources, respectively; a flip-flop circuit electrically connected between first and second terminal means comprising two fuses and further comprising two transistors each having a control region, each fuse being in a load circuit of one of the transistors with the control region of each transistors being electrically connected to the load circuit of the other transistor, each fuse providing a conductive path of a selected conductivity which is of a relatively high conductivity in the form in which the fuse is initially provided but of a relatively low conductivity if blown; and an initializing transistor electrically connected between a selected one of said first and second terminal means and a selected one of said transistor control regions for selectively providing a current path therebetween, and whereby, if the detection circuit is electrically energized, a first predetermined signal is provided if the fuses are conducting and a second predetermined signal is provided if the fuses are blown.

Claim 6

A fuse status detection circuit for detecting the status of a fuse, the circuit comprising: first and second terminal means adapted for electrical connection to first and second voltage sources, respectively; a flip-flop circuit electrically connected between first and second terminal means comprising two fuses and further comprising two transistors each having a control region, each fuse being in a load circuit of one of the transistors with the control region of each transistors being electrically connected to the load circuit of the other transistor, each fuse providing a conductive path of a selected conductivity which is of a relatively high conductivity in the form in which the fuse is initially provided but of a relatively low conductivity if blown; and an initializing transistor electrically connected between a selected one of said first and second terminal means and a selected one of said transistor control regions for selectively providing a current path therebetween, and whereby, if the detection circuit is electrically energized, a first predetermined signal is provided if the fuses are conducting and a second predetermined signal is provided if the fuses are blown.

Claim 7

A fuse status detection circuit, the circuit comprising: first and second terminal means adapted for electrical connection to first and second voltage sources, respectively; first and second transistors each having first and second terminating regions and a control region therein by which it is capable of being directed to effectively provide a conductive path of a selected conductivity between its said first and second terminating regions, the first transistor first terminating region being electrically connected to the second transistor control region, the first transistor second terminating region being electrically connected to the second terminal means, the second transistor first terminating region being electrically connected to the first terminal means, and the second transistor second terminating region being electrically connected to the first transistor control region; and an initializing transistor electrically connected between a selected one of the first and second terminal means and a selected one of the first and second transistor control regions for selectively providing a current path therebetween; and first and second fuses each having a first and second terminating region between which a conductive path of a selected conductivity is provided and being of a relatively high conductivity in the form in which it is initially provided but of a relatively low conductivity if blown, the first fuse being electrically connected between the first terminal means and the second transistor control region, and the second fuse being electrically connected between the first transistor control region and the second terminal means, whereby, if the detection circuit is electrically energized, a first predetermined signal is provided if the first and second fuses are both conducting, and a second predetermined signal is provided if the first and second fuses are blown.

Claim 8

A fuse status detection circuit, the circuit comprising: first and second terminal means adapted for electrical connection to first and second voltage sources, respectively; first and second transistors each having first and second terminating regions and a control region therein by which it is capable of being directed to effectively provide a conductive path of a selected conductivity between its said first and second terminating regions, the first transistor first terminating region being electrically connected to the second transistor control region, the first transistor second terminating region being electrically connected to the second terminal means, the second transistor first terminating region being electrically connected to the first terminal means, and the second transistor second terminating region being electrically connected to the first transistor control region; and an initializing transistor electrically connected between a selected one of the first and second terminal means and a selected one of the first and second transistor control regions for selectively providing a current path therebetween; and first and second fuses each having a first and second terminating region between which a conductive path of a selected conductivity is provided and being of a relatively high conductivity in the form in which it is initially provided but of a relatively low conductivity if blown, the first fuse being electrically connected between the first terminal means and the second transistor control region, and the second fuse being electrically connected between the first transistor control region and the second terminal means, whereby, if the detection circuit is electrically energized, a first predetermined signal is provided if the first and second fuses are both conducting, and a second predetermined signal is provided if the first and second fuses are blown.

Claim 9

The apparatus of claim 1 wherein one of the transistors is a p channel MOS transistor and the other transistor is a n channel MOS transistor.

Claim 10

A fuse detection circuit which comprises: a first transistor having a drain, a gate and a source; a second transistor having a drain, a gate and a source; means for connecting the drain of the first transistor to the gate of the second transistor; means for connecting the gate of the first transistor to the drain of the second transistor; an initializing transistor; means for connecting said initializing transistor between the drain and the source of at least one of said first or second transistors; a pair of fuses; means for connecting one of the fuses between the gate of the first transistor and the source of the first transistor; means for connecting the second fuse between the gate of the second transistor and the source of the second transistor; means for connecting a high positive voltage to the source of the first transistor; means for connecting ground potential to the source of the second transistor; output means connected to the drain of either transistor for providing an output signal; and said first and second transistors, said initializing transistor and fuses having parameters selected so that, when the fuses are conductive, the output means provides a first predetermined output signal and so that, when the fuses are nonconductive, the output means provides a second predetermined output signal.

Claim 11

A fuse detection circuit which comprises: a first transistor having a drain, a gate and a source; a second transistor having a drain, a gate and a source; means for connecting the drain of the first transistor to the gate of the second transistor; means for connecting the gate of the first transistor to the drain of the second transistor; an initializing transistor; means for connecting said initializing transistor between the drain and the source of at least one of said first or second transistors; a pair of fuses; means for connecting one of the fuses between the gate of the first transistor and the source of the first transistor; means for connecting the second fuse between the gate of the second transistor and the source of the second transistor; means for connecting a high positive voltage to the source of the first transistor; means for connecting ground potential to the source of the second transistor; output means connected to the drain of either transistor for providing an output signal; and said first and second transistors, said initializing transistor and fuses having parameters selected so that, when the fuses are conductive, the output means provides a first predetermined output signal and so that, when the fuses are nonconductive, the output means provides a second predetermined output signal.

Claim 12

A fuse status detection circuit, the circuit comprising: first and second terminal means adapted for electrical connection to first and second voltage sources, respectively; first and second transistors each having first and second terminating regions and a control region therein by which it is capable of being directed to effectively provide a conductive path of a selected conductivity between its said first and second terminating regions, the first transistor first terminating region being electrically connected to the second transistor control region, the first transistor second terminating region being electrically connected to the second terminal means, the second transistor first terminating region being electrically connected to the first terminal means, and the second transistor second terminating region being electrically connected to the first transistor control region; and an initializing element electrically connected between a selected one of the first and second terminal means and a selected on of the first and second transistor control regions, wherein said initializing element includes a capacitor comprising a thin film metal layer which overlies and is separated from a doped semiconductor region by an insulating layer; and first and second fuses each having a first and second terminating region between which a conductive path of a selected conductivity is provided and being of a relatively high conductivity in the form in which it is initially provided but of a relatively low conductivity if blown, the first fuse being electrically connected between the first terminal means and the second transistor control region, and the second fuse being electrically connected between the first transistor control region and the second terminal means, whereby, if the detection circuit is electrically energized, a first predetermined signal is provided if the first and second fuses are both conducting, and a second predetermined signal is provided if the first and second fuses are blown.

Claim 13

A fuse status detection circuit, the circuit comprising: first and second terminal means adapted for electrical connection to first and second voltage sources, respectively; first and second transistors each having first and second terminating regions and a control region therein by which it is capable of being directed to effectively provide a conductive path of a selected conductivity between its said first and second terminating regions, the first transistor first terminating region being electrically connected to the second transistor control region, the first transistor second terminating region being electrically connected to the second terminal means, the second transistor first terminating region being electrically connected to the first terminal means, and the second transistor second terminating region being electrically connected to the first transistor control region; and an initializing element electrically connected between a selected one of the first and second terminal means and a selected on of the first and second transistor control regions, wherein said initializing element includes a capacitor comprising a thin film metal layer which overlies and is separated from a doped semiconductor region by an insulating layer; and first and second fuses each having a first and second terminating region between which a conductive path of a selected conductivity is provided and being of a relatively high conductivity in the form in which it is initially provided but of a relatively low conductivity if blown, the first fuse being electrically connected between the first terminal means and the second transistor control region, and the second fuse being electrically connected between the first transistor control region and the second terminal means, whereby, if the detection circuit is electrically energized, a first predetermined signal is provided if the first and second fuses are both conducting, and a second predetermined signal is provided if the first and second fuses are blown.

Claim 14

The apparatus of claim 8 wherein the initializing element comprises a capacitor.

Claim 15

The apparatus of claim 8 wherein at least one of the fuses comprises a member of conductive polysilicon.

Claim 16

The apparatus of claim 8 wherein one of the transistors is a p channel MOS transistor and the other transistor is a n channel MOS transistor.

Claim 17

A fuse detection circuit which comprises: a first transistor having a drain, a gate and a source; a second transistor having a drain, a gate and a source; means for connecting the drawin of the first transistor to the gate of the second transistor; means for connecting the gate of the first transistor to the drain of the second transistor; an initializing element including a capacitor, said capacitor comprising a thin film metal layer which overlies and is separated from a doped semiconductor region by an insulating layer; means for connecting the initializing element between the drain and the source of at least one of the transistors; a pair of fuses; means for connecting one of the fuses between the gate of the first transistor and the source of the first transistor; means for connecting the second fuse between the gate of the second transistor and the source of the second transistor; means for connecting a high positive voltage to the source of the first transistor; means for connecting ground potential to the source of the second transistor; output means connected to the drain of either transistor for providing an output signal; and the transistors, initializing element and fuses having parameters selected so that, when the fuses are conductive, the output means provides a first predetermined output signal and so that, when the fuses are nonconductive, the output means provides a second predetermined output signal.

Claim 18

A fuse detection circuit which comprises: a first transistor having a drain, a gate and a source; a second transistor having a drain, a gate and a source; means for connecting the drawin of the first transistor to the gate of the second transistor; means for connecting the gate of the first transistor to the drain of the second transistor; an initializing element including a capacitor, said capacitor comprising a thin film metal layer which overlies and is separated from a doped semiconductor region by an insulating layer; means for connecting the initializing element between the drain and the source of at least one of the transistors; a pair of fuses; means for connecting one of the fuses between the gate of the first transistor and the source of the first transistor; means for connecting the second fuse between the gate of the second transistor and the source of the second transistor; means for connecting a high positive voltage to the source of the first transistor; means for connecting ground potential to the source of the second transistor; output means connected to the drain of either transistor for providing an output signal; and the transistors, initializing element and fuses having parameters selected so that, when the fuses are conductive, the output means provides a first predetermined output signal and so that, when the fuses are nonconductive, the output means provides a second predetermined output signal.

Claim 19

The apparatus of claim 12 wherein the output means comprises means for generating a first predetermined signal having a signal level which bears a predetermined relationship to the supply voltage.

Claim 20

The apparatus of claim 12 wherein the output means comprises means for generating a first predetermined signal having a voltage level which is substantially equal to the supply voltage.

Claim 21

The apparatus of claim 12 wherein the first transistor is a p channel MOS transistor and the second transistor is a n channel MOS transistor.

Claim 22

The apparatus of claim 12 wherein the transistors comprise CMOS technology with the first transistor being p channel and the second transistor being n channel.

Claim 23

The apparatus of claim 12 wherein the initializing element is connected in parallel with the first transistor.

Claim 24

The apparatus of claim 12 wherein the initializing element is connected in parallel with the second transistor.

Claim 25

The apparatus of claim 12 wherein an initializing element is connected in parallel with both first and second transistors.

Claim 26

The apparatus of claim 12 wherein each fuse comprises a member of conductive polysilicon.

Claim 27

The apparatus of claim 12 wherein the initializing element comprises a capacitor.