Data processing system with a fast interrupt

Claim 1

A data processing system wherein an emergency or top priority interrupt signal will by-pass a priority-level comparison to access an addressed processing unit, comprising: a plurality of interrupting units and a plurality of processing units coupled in common to a system bus for asynchronously transferring commands between said plurality of interrupting units and each of said plurality of processing units during different bus cycles of operation, and further including: command generating means coupled to said bus for applying commands to said bus during bus cycles of operation granted to said processing units, each of said commands including an address field coded to specify a channel number indicating an address of a processing unit to receive said command, said command further including a control field including a memory reference signal indicating that said address field is coded to specify said channel number, and an interrupt type signal in a first state specifying a normal interrupt or an interrupt type signal in a second state specifying a fast interrupt, said fast interrupt, second state signal by-passing a priority level comparison and directly accessing an addressed processing unit; channel decoder means coupled to said bus for generating an output signal upon detecting that said channel number is assigned to said processing unit and said memory reference signal has been applied to said bus by a respective one of said processing units; logic array means coupled to said bus and said channel decoder means and responsive to said interrupt type signal in said second state specifying said fast interrupt, said output signal and a busy signal in a first state generated by a flip flop means for generating both a first acknowledge signal indicating that said processing unit is executing said command, and a set busy signal, said logic array means being further responsive to said interrupt type signal in said first state specifying said normal interrupt and said output signal for generating a compare signal; comparison means coupled to said bus and said logic array means and responsive to said compare signal, said comparison means comparing a current interrupt priority level with a priority level of a command already being executed by a processing unit, and in response thereto, generating a second acknowledge signal if said current interrupt priority level is greater than said executed command interrupt priority level and generating a second not acknowledge signal if said current interrupt priority level is not greater than said executed command interrupt priority level; busy means coupled to said bus and said logic array means and including said flip flop means responsive to an address signal included in said command and said set busy signal for generating said busy signal in a second state; said logic array means being further coupled to said bus, said channel decoder means and said busy means and responsive to said interrupt type signal in said first state, said output signal from a subsequent command and said busy signal in said second state for generating a first not acknowledge signal indicating that said processing unit is not executing said command; and response means coupled to said logic array means and said bus and responsive to said first acknowledge signal for sending an acknowledge response signal to said interrupting unit associated with said fast interrupt signal, and responsive to said first not acknowledge signal for sending a not acknowledge response signal to said interrupting unit associated with said normal interrupt signal, said response means further coupled to said comparison means and said bus and responsive to said second acknowledge signal for generating a second acknowledge response signal, and responsive to said second not acknowledge signal for generating a second not acknowledge response signal.