US4847868A
Expired / Lapsed
US
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Non-coherent pattern detection
Assignee: Teridian Semiconductor Corp
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Filing: 1988-02-22
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Granted: 1989-07-11
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Expires: 2008-02-22
Abstract
Abstract The present invention is directed to a digital non-coherent pattern detection scheme in which spectral analysis of phase encoded signals is utilized to provide pattern recognition. The present invention is relatively insensitive to the power level of incoming signals. Since the power level is easily detected and determined, the present invention allows the various algorithms to operate quickly. Further, utilizing the magnitude samples of the incoming signal result in a pattern detection scheme that is independent of modulation technique. The present invention utilizes the concept of spectral analysis to determine spectral lines which are present in phase encoded signals. A phase encoded signal such as a DPSK or QAM having an implicit pattern contained therein, which results in unique spectral lines. By detecting the spectral lines in certain combinations, the phase encoded pattern being sent may be identified. For example, "unscrambled mark", "S1", and other patterns may be identified using the method of the present invention. In operation, a plurality of receive channels are implemented to detect energy levels at specific frequencies and thereby identify spectral lines. The input signal is demodulated with one of a plurality of modulating frequencies F 0 -F n in each receive channel, chosen to translate the input spectra signal to baseband. The demodulated signal is low pass filtered and the filtered output is squared, generating a power signal. In the preferred embodiment, the power signal is filtered again to obtain a stochastic average. This averaged signal is coupled to an energy detect block. If energy at the desired spectra is present and of sufficient magnitude, a digital "one" is provided as output, if sufficient energy is detected, a digital "zero" is provided as output. A logical "one" is provided at the output representing the specific pattern detected as indicated by the digital word.
Inventors
- 👤 Dave Hedberg
- 👤 Paul Hurst
- 👤 Steve Levy
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 11:59
CPC Classifications
H; H04; H04L; H04L27/00; H04L27/18; H04L27/22; H04L27/233; H04L27/32; H04L27/34; H04L27/38
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
187 words
A circuit for detecting and identifying scrambled and unscrambled non-coherent patterns in an input signal comprising: at least one receiving channel for receiving said input signal and detecting one of a plurality of spectral lines; said receiving channel comprising demodulating means coupled to said input signal and to one of a plurality of modulating signals, said demodulating means translating said input signal to a baseband signal; first filter means coupled to said baseband signal for filtering said baseband signal and providing a first output in a desired frequency range; squaring means coupled to said first output for squaring said first output and providing a power signal; second filter means coupled to said power signal for filtering and averaging said power signal, said second filter means providing a second output having a magnitude; detection means coupled to said second output for outputting a digital signal when said magnitude of said second output is greater than a desired level; decoding means coupled to said digital signal for decoding said digital signal and providing one of a plurality of pattern detect signals depending on the value of said digital signal.
Claim 2
Dependent Claim
187 words
A circuit for detecting and identifying scrambled and unscrambled non-coherent patterns in an input signal comprising: at least one receiving channel for receiving said input signal and detecting one of a plurality of spectral lines; said receiving channel comprising demodulating means coupled to said input signal and to one of a plurality of modulating signals, said demodulating means translating said input signal to a baseband signal; first filter means coupled to said baseband signal for filtering said baseband signal and providing a first output in a desired frequency range; squaring means coupled to said first output for squaring said first output and providing a power signal; second filter means coupled to said power signal for filtering and averaging said power signal, said second filter means providing a second output having a magnitude; detection means coupled to said second output for outputting a digital signal when said magnitude of said second output is greater than a desired level; decoding means coupled to said digital signal for decoding said digital signal and providing one of a plurality of pattern detect signals depending on the value of said digital signal.
Claim 3
Dependent Claim
17 words
The circuit of claim 1 wherein said first filter means comprises an nth order low pass filter.
Claim 4
Dependent Claim
9 words
The circuit of claim 1 having muliple receiving channels.
Claim 5
Dependent Claim
30 words
The circuit of claim 3 wherein each of said receiving channels provides a digital signal to said decoding means such that said digital signals comprise a multiple bit digital word.
Claim 6
Dependent Claim
35 words
The circuit of claim 1 wherein said digital signal comprises a first logical value when said magnitude exceeds said desired level and a second logical value when said magnitude is less than said desired level.
Claim 7
Dependent Claim
233 words
A circuit for detecting and identifying scrambled and unscrambled non-coherent patterns of an input signal comprising: a plurality of receiving channels for receiving said input signal and detecting one of a plurality of spectral lines; each of said receive channels comprising; demodulating means coupled to said input signal and to one of a plurality of modulating frequencies, said demodulating means translating said input signal to a baseband signal; first filter means coupled to said baseband signal for filtering said baseband signal and providing a first output signal in a desired frequency range; squaring means coupled to said first output signal for squaring said first output signal and providing a power signal; second filter means coupled to said power signal for filtering and averaging said power signal and providing a second output signal having a magnitude; detection means coupled to said second output signal for detecting said magnitude of said second output signal and providing a digital signal having a logical value dependent on said magnitude of said second output signal; combining means coupled to said digital signal from each of said receiving channels for combining said digital signals into a digital word; decoding means coupled to said digital word for decoding said digital word and providing one of a plurality of outputs dependent on a value of said digital word, each of said plurality of outputs representing one of said plurality of patterns.
Claim 8
Dependent Claim
233 words
A circuit for detecting and identifying scrambled and unscrambled non-coherent patterns of an input signal comprising: a plurality of receiving channels for receiving said input signal and detecting one of a plurality of spectral lines; each of said receive channels comprising; demodulating means coupled to said input signal and to one of a plurality of modulating frequencies, said demodulating means translating said input signal to a baseband signal; first filter means coupled to said baseband signal for filtering said baseband signal and providing a first output signal in a desired frequency range; squaring means coupled to said first output signal for squaring said first output signal and providing a power signal; second filter means coupled to said power signal for filtering and averaging said power signal and providing a second output signal having a magnitude; detection means coupled to said second output signal for detecting said magnitude of said second output signal and providing a digital signal having a logical value dependent on said magnitude of said second output signal; combining means coupled to said digital signal from each of said receiving channels for combining said digital signals into a digital word; decoding means coupled to said digital word for decoding said digital word and providing one of a plurality of outputs dependent on a value of said digital word, each of said plurality of outputs representing one of said plurality of patterns.
Claim 9
Dependent Claim
13 words
The circuit of claim 6 wherein said plurality of receiving channels comprises four.
Claim 10
Dependent Claim
15 words
The circuit of claim 7 wherein said digital word comprises a four bit digital word.
Claim 11
Dependent Claim
17 words
The circuit of claim 6 wherein said first filter means comprises a second order low pass filter.
Claim 12
Independent Claim
138 words
A method for detecting a plurality of scrambled and unscrambled non-coherent patterns of an input signal comprising the steps of: modulating said input signal with a modulating function to translate said input signal to a baseband signal; filtering said baseband signal to provide a first output signal in a desired frequency range; generating a power signal from said first output signal; averaging said power signal over a first number of samples and providing a second output signal having a magnitude; detecting said magnitude and providing a digital signal having a first logical value when said magnitude is greater than a desired level; decoding said digital signal and providing one of a plurality of pattern detect signals depending on the value of said digital signal, each of said pattern detect signals representing one of said plurality of said patterns.
Claim 13
Independent Claim
138 words
A method for detecting a plurality of scrambled and unscrambled non-coherent patterns of an input signal comprising the steps of: modulating said input signal with a modulating function to translate said input signal to a baseband signal; filtering said baseband signal to provide a first output signal in a desired frequency range; generating a power signal from said first output signal; averaging said power signal over a first number of samples and providing a second output signal having a magnitude; detecting said magnitude and providing a digital signal having a first logical value when said magnitude is greater than a desired level; decoding said digital signal and providing one of a plurality of pattern detect signals depending on the value of said digital signal, each of said pattern detect signals representing one of said plurality of said patterns.
Claim 14
Dependent Claim
38 words
The method of claim 10 further including performing the steps of claim 10 for a plurality of modulating function such that a plurality of said digital signals are provided and combining said plurality signals into a digital word.
Claim 15
Dependent Claim
15 words
The method of claim 11 wherein said digital word is provided to said decoding means.
Claim 16
Dependent Claim
21 words
The method of claim 10 wherein said step of generating said power signal is performed by squaring said first output signal.
Claim 17
Dependent Claim
25 words
The method of claim 10 wherein said step of averaging said power signal is performed by low pass filtering four samples of said power signal.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-07-10 | 1993-01-09 | 1993-07-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-07-10 | 1997-01-09 | 1997-07-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-07-10 | 2001-01-09 | 2001-07-11 | $7700.00 | Window Closed / Lapsed |