US4847873A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Interface circuit
Assignee: Victor Company of Japan Ltd
•
Filing: 1987-06-11
•
Granted: 1989-07-11
•
Expires: 2007-06-11
Abstract
Abstract An interface circuit transmits a digital data signal from a transmission unit to a reception unit via a coupling device. The interface circuit includes a device removing jitter components from the digital data signal. The interface circuit also includes a device removing high frequency noise components from the digital data signal. The jitter removing device and the noise removing device may be disposed in either of the transmission unit and the reception unit.
Inventors
- 👤 Toshiharu Kuwaoka
- 👤 Minoru Kanai
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 05:59
CPC Classifications
H; H04; H04L; H04L25/00; H04L25/02; H04L25/20; H04L25/26
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
179 words
An interface circuit for transmitting a digital data signal from a transmission unit to a reception unit, the interface circuit comprising: (a) photo coupling means optically connecting the transmission unit and the reception unit, the photo coupling means including a photo emitter and a photo receptor connected via a optical path, the photo emitter being disposed in the transmission unit and provided with a transmission digital data signal, said photo emitter generating an optical signal corresponding to the transmission digital data signal, the photo receptor disposed in the reception unit and receiving the optical signal the photo receptor converting the optical signal into a corresponding reception digital signal; and (b) means for preventing the reception digital signal from being contaminated by jitter components and high frequency noise components; the preventing means comprising means for generating short pulses in synchronism with a transmission digital data signal, and means for enabling the receptor with the short pulses, wherein the receptor samples the optical signal and converts the sampled optical signal into the reception digital signal in response to said short pulses.
Claim 2
Dependent Claim
179 words
An interface circuit for transmitting a digital data signal from a transmission unit to a reception unit, the interface circuit comprising: (a) photo coupling means optically connecting the transmission unit and the reception unit, the photo coupling means including a photo emitter and a photo receptor connected via a optical path, the photo emitter being disposed in the transmission unit and provided with a transmission digital data signal, said photo emitter generating an optical signal corresponding to the transmission digital data signal, the photo receptor disposed in the reception unit and receiving the optical signal the photo receptor converting the optical signal into a corresponding reception digital signal; and (b) means for preventing the reception digital signal from being contaminated by jitter components and high frequency noise components; the preventing means comprising means for generating short pulses in synchronism with a transmission digital data signal, and means for enabling the receptor with the short pulses, wherein the receptor samples the optical signal and converts the sampled optical signal into the reception digital signal in response to said short pulses.
Claim 3
Dependent Claim
113 words
The interface circuit of claim 1 wherein the jitter removing means and the noise removing means comprise a control driver operating at a timing outside a period during which jitter components of the digital data signal tend to occur, means for generating a processed signal in accordance with the operation timing of the control driver while a transmission element of the coupling device remains active, a D flip-flop having a data input terminal receiving the processed signal and having a clock input terminal, means for generating a clock timing concurrent with the operation timing of the control driver, and means for applying the clock to the clock input terminal of the D flip-flop.
Claim 4
Dependent Claim
34 words
The interface circuit of claim 1 wherein said receptor-enabling-means comprises switching means connected in series with the receptor for selectively allowing and interrupting a current through the receptor in response to said short pulses.
Claim 5
Dependent Claim
38 words
The interface circuit of claim 1 where in said receptor-enabling-means comprises switching means connected in parallel with the receptor for selectively unshunting and shunting an output of the receptor to a ground in response to said short pulses.
References Cited (Backward Citations)
GB1061985A
Cited
GB1291992A
Cited
US3794841A
Cited
US4054747A
Cited
US4211920A
Cited
US4168427A
Cited
US4228323A
Cited
EP0044685A1
Cited
US4501022A
Cited
US4596048A
Cited
US4598412A
Cited
US4710976A
Cited
US4697275A
Cited
GB2168575A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-07-10 | 1993-01-09 | 1993-07-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-07-10 | 1997-01-09 | 1997-07-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-07-10 | 2001-01-09 | 2001-07-11 | $7700.00 | Window Closed / Lapsed |