US4849657A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Fault tolerant integrated circuit design
Assignee: SYNERTEK Inc A DE CORP
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Filing: 1984-09-17
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Granted: 1989-07-18
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Expires: 2004-09-17
Abstract
Abstract A fault-tolerant digital integrated circuit includes functionally identical circuit blocks, each of such identical circuit blocks having an input region and an output region. The input regions receive identical input signals and the output regions are electrically connected to a combining logic gate, typically an OR gate. In this way a defect in any one of the identical blocks will not prevent operation of the circuit.
Inventors
- 👤 Conrad J. Boisvert
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 11:55
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/007; H03K19/0075
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
113 words
A fault-tolerant semiconductor integrated circuit comprising: first digital circuit element means having input means and output means; second digital circuit element means having input means and output means, said first and second digital circuit element means being functionally identical and said first digital circuit element input means being electrically connected to said second digital circuit input means; and combining logic gate means having a plurality of input means, at least one of said combining logic gate means input means being electrically connected to said first digital circuit element output means and at least one of said combining logic gate means input means being electrically connected to said second digital circuit element output means.
Claim 2
Dependent Claim
113 words
A fault-tolerant semiconductor integrated circuit comprising: first digital circuit element means having input means and output means; second digital circuit element means having input means and output means, said first and second digital circuit element means being functionally identical and said first digital circuit element input means being electrically connected to said second digital circuit input means; and combining logic gate means having a plurality of input means, at least one of said combining logic gate means input means being electrically connected to said first digital circuit element output means and at least one of said combining logic gate means input means being electrically connected to said second digital circuit element output means.
Claim 3
Dependent Claim
17 words
The circuit of claim 1 wherein said combining logic gate means includes a logical OR gate means.
Claim 4
Dependent Claim
22 words
The circuit of claim 1 wherein each of said first and second digital circuit element means includes a plurality of flip-flop means.
Claim 5
Dependent Claim
17 words
The circuit of claim 3 wherein said combining logic gate means includes a logical OR gate means.
Claim 6
Dependent Claim
20 words
The circuit of claim 1 wherein each of said first and second digital circuit elements includes a shift register means.
Claim 7
Dependent Claim
17 words
The circuit of claim 5 wherein said combining logic gate means includes a logical OR gate means.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-07-17 | 1993-01-16 | 1993-07-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-07-17 | 1997-01-16 | 1997-07-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-07-17 | 2001-01-16 | 2001-07-18 | $7700.00 | Window Closed / Lapsed |