US4849662A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Switched-capacitor filter having digitally-programmable capacitive element
Assignee: TECHNOLOGY FUNDING SECURED INVESTORS A CA LP
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Filing: 1986-04-14
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Granted: 1989-07-18
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Expires: 2006-04-14
Abstract
Abstract A method and circuitry for time-sharing a digitally-programmable capacitive element, particularly in conjunction with a switched-capacitor filter circuit. The method includes: selecting a first capacitance value for the capacitive element; initializing the charge on the capacitive element; connecting the capacitive element to first preselected nodes of an electronic circuit; disconnecting the capacitive element from the first preselected nodes of after any charge transfer has substantially been completed; changing the capacitance of the capacitive element to a new desired value; initializing the charge on the capacitive element; and then connecting the capacitive element to other preselected nodes of the electronic circuit. A biquad switched-capacitor filter circuit is configured to use such method in its operation.
Inventors
- 👤 Douglas R. Holberg
- 👤 Eric J. Swanson
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 02:43
CPC Classifications
H; H03; H03H; H03H19/00
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
145 words
A method for multiplexing a digitally-programmable capacitive element in a switched-capacitor filter circuit, said switched-capacitor filter circuit having a differential amplifier and a ground node, comprising: a. coupling said digitally-progammable capacitive element between said ground node and the inverting input of said differential amplifier while digitally selecting a first desired capacitance value for said capacitive element; and thereafter performing the following steps in the same sampling cycle, b. uncoupling said digitally-programmable capacitive element from between said ground node and the inverting input of said differential amplifier; and thereafter performing the following step in the same sampling cycle, c. coupling said digitally-programmable capacitive element between the inverting input of said differential amplifier and the output of said differential amplifier while digitally selecting a second desired capacitance value for said capacitive element, said second desired capacitive value being different from that of said first desired capacitance value.
Claim 2
Independent Claim
145 words
A method for multiplexing a digitally-programmable capacitive element in a switched-capacitor filter circuit, said switched-capacitor filter circuit having a differential amplifier and a ground node, comprising: a. coupling said digitally-progammable capacitive element between said ground node and the inverting input of said differential amplifier while digitally selecting a first desired capacitance value for said capacitive element; and thereafter performing the following steps in the same sampling cycle, b. uncoupling said digitally-programmable capacitive element from between said ground node and the inverting input of said differential amplifier; and thereafter performing the following step in the same sampling cycle, c. coupling said digitally-programmable capacitive element between the inverting input of said differential amplifier and the output of said differential amplifier while digitally selecting a second desired capacitance value for said capacitive element, said second desired capacitive value being different from that of said first desired capacitance value.
Claim 3
Dependent Claim
337 words
A biquad switched-capacitor filter circuit having an input node, having an output node, and having a ground node, comprising: a. a first differential amplifier, the non-inverting input of said first differential amplifier being coupled to ground; b. a first feedback capacitor coupled between the output and the inverting input of said first differential amplifier; c. a second differential amplifier, the non-inverting input of said second differential amplifier being coupled to ground, the output of said second differential amplifier being coupled to said output node of said switched-capacitor filter circuit; d. a second feedback capacitor coupled between the output and the inverting input of said second differential amplifier; e. a first digitally-programmable capacitive element having first and second terminals; f. control and timing logic circuitry for controlling the operation of said switched-capacitor filter circuit; g. a first switch means responsive to said control and timing logic circuitry for selectively coupling said first terminal of said first digitally-programmable capacitive element to: (1) an open circuit, (2) the input node of the switched-capacitor filter circuit, or (3) ground; h. a second switch means responsive to said control and timing logic circuitry for selectively coupling said second terminal of said first digitally-programmable capacitive element to: (1) an open circuit, (2) the inverting input of said second differential amplifier, (3) the inverting input of said first differential amplifier, or (4) ground; i. a second digitally-programmable capacitive element having first and second terminals; j. a third switch means responsive to said control and timing logic circuitry for selectively coupling said first terminal of said second digitally-programmable capacitive element to: (1) an open circuit, (2) the output of said first differential amplifier, (3) the output of said second differential amplifier, or (4) ground; k. a fourth switch means responsive to said control and timing logic circuitry for selectively coupling said second terminal of said second digitally-programmable capacitive element to: (1) an open circuit, (2) the inverting input of said second differential amplifier, (3) the inverting input of said first differential amplifier, or (4) ground.
Claim 4
Dependent Claim
337 words
A biquad switched-capacitor filter circuit having an input node, having an output node, and having a ground node, comprising: a. a first differential amplifier, the non-inverting input of said first differential amplifier being coupled to ground; b. a first feedback capacitor coupled between the output and the inverting input of said first differential amplifier; c. a second differential amplifier, the non-inverting input of said second differential amplifier being coupled to ground, the output of said second differential amplifier being coupled to said output node of said switched-capacitor filter circuit; d. a second feedback capacitor coupled between the output and the inverting input of said second differential amplifier; e. a first digitally-programmable capacitive element having first and second terminals; f. control and timing logic circuitry for controlling the operation of said switched-capacitor filter circuit; g. a first switch means responsive to said control and timing logic circuitry for selectively coupling said first terminal of said first digitally-programmable capacitive element to: (1) an open circuit, (2) the input node of the switched-capacitor filter circuit, or (3) ground; h. a second switch means responsive to said control and timing logic circuitry for selectively coupling said second terminal of said first digitally-programmable capacitive element to: (1) an open circuit, (2) the inverting input of said second differential amplifier, (3) the inverting input of said first differential amplifier, or (4) ground; i. a second digitally-programmable capacitive element having first and second terminals; j. a third switch means responsive to said control and timing logic circuitry for selectively coupling said first terminal of said second digitally-programmable capacitive element to: (1) an open circuit, (2) the output of said first differential amplifier, (3) the output of said second differential amplifier, or (4) ground; k. a fourth switch means responsive to said control and timing logic circuitry for selectively coupling said second terminal of said second digitally-programmable capacitive element to: (1) an open circuit, (2) the inverting input of said second differential amplifier, (3) the inverting input of said first differential amplifier, or (4) ground.
Claim 5
Dependent Claim
63 words
A biquad switched-capacitor filter circuit according to claim 2 and further comprising a sample-and-hold circuit having an input and an output, the input of said sample-and-hold circuit being coupled to said output node of said switched-capacitor filter circuit, and the output of said sample-and-hold circuit being selectively coupled by said third switch means to said first terminal of said second digitally-programmable capacitive element.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-07-17 | 1993-01-16 | 1993-07-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-07-17 | 1997-01-16 | 1997-07-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-07-17 | 2001-01-16 | 2001-07-18 | $7700.00 | Window Closed / Lapsed |