Semiconductor memorizing device

Claim 2

A semiconductor memory comprising: a first selection line coupled to a first memory cell and a second selection line coupled to a second memory cell; a selection means which selects either one of said selection lines, said selection means having a selection circuit which optionally selects said first selection line or said second selection line when an address signal corresponding to said first selection line is aligned with a predetermined address signal; a memory means for memorizing said predetermined address signal; and means for detecting an alignment of said address signal with said predetermined address signal, wherein said first selection line is a word line to which a primary memory cell is connected, and said second selection line is a word line to which a stand-by memory cell is connected so that said first memory cell is said primary memory cell and said second memory cell is said stand-by memory cell, and further wherein said predetermined address signal is an address signal which corresponds to a word line to which a defective memory cell is connected.

Claim 3

A semiconductor memory according to claim 1, further comprising an input terminal through which a signal for controlling said selection circuit is provided.

Claim 4

A semiconductor memory according to claim 2, wherein said memory means comprises a read only memory.

Claim 5

A semiconductor memory according to claim 3, wherein said read only memory comprises a plurality of fuses which are programmed with said predetermined address signal in accordance with whether the respective fuses are in an open or closed condition.

Claim 6

A semiconductor memory according to claim 4, wherein said read only memory includes a circuit for cutting said fuses by passing a predetermined current therethrough for programming said read only memory.

Claim 7

A semiconductor memory according to claim 5, wherein said fuses are programmed by laser cutting.

Claim 8

A semiconductor memory comprising: a memory array having a plurality of memory cells respectively arranged along predetermined lines in accordance with predetermined addresses; a spare memory array having a plurality of spare memory cells arranged along predetermined spare lines; a redundant address switching circuit including means for storing the addresses of known defective memory cells in said memory array, means for comparing an address signal from outside said semiconductor memory with said stored addresses, and means for switching said address signal from outside said semiconductor memory to one of said predetermined spare lines in said spare memory array; and means for overriding the switching means in said redundant address switching circuit to permit access to said known defective memory cell in said memory array by an address signal from outside said semiconductor memory.

Claim 9

A semiconductor memory comprising: a memory array having a plurality of memory cells respectively arranged along predetermined lines in accordance with predetermined addresses; a spare memory array having a plurality of spare memory cells arranged along predetermined spare lines; a redundant address switching circuit including means for storing the addresses of known defective memory cells in said memory array, means for comparing an address signal from outside said semiconductor memory with said stored addresses, and means for switching said address signal from outside said semiconductor memory to one of said predetermined spare lines in said spare memory array; and means for overriding the switching means in said redundant address switching circuit to permit access to said known defective memory cell in said memory array by an address signal from outside said semiconductor memory.

Claim 10

A semiconductor memory according to claim 7, wherein said overriding means comprises a gate means for receiving an output of the comparator means and for receiving a control signal, wherein said gate means includes means for only allowing said switching means to operate to switch to said predetermined spare line of said spare memory array if said comparing means indicates that the address signal received from outside said semiconductor memory corresponds to the stored address of a defective memory cell and if said control signal has a predetermined level.

Claim 11

A semiconductor memory according to claim 8, wherein said address storing means comprises a read only memory.

Claim 12

A semiconductor memory according to claim 9, wherein said read only memory comprises a plurality of fuses which are programmed with the known address of a defective memory cell in said memory array in accordance with whether the respective fuses are in an open or closed condition.

Claim 13

A semiconductor memory according to claim 10, wherein said read only memory includes a circuit for cutting said fuses by passing a predetermined current therethrough for programming said read only memory.

Claim 14

A semiconductor memory according to claim 10, wherein said fuses are programmed by laser cutting.

Claim 15

A semiconductor memory according to claim 7, wherein said address storing means comprises a read only memory.

Claim 16

A semiconductor memory according to claim 13, wherein said read only memory comprises a plurality of fuses which are programmed with the known address of a defective memory cell in said memory array in accordance with whether the respective fuses are in an open or closed condition.

Claim 17

A semiconductor memory according to claim 14, wherein said read only memory includes a circuit for cutting said fuses by passing a predetermined current therethrough for programming said read only memory.

Claim 18

A semiconductor memory according to claim 14, wherein said fuses are programmed by laser cutting.

Claim 19

A semiconductor memory comprising: a memory array having a plurality of memory cells and a plurality of selecting lines coupled to said memory cells, respectively; a spare memory array having a spare memory cell and a spare selecting line coupled to said spare memory cell; an address terminal means for receiving an address signal; selecting means for selecting one of said selecting lines in accordance with an address signal received at said address terminal means; storing means for storing an address of a known defective memory cell in said memory array; detecting means for detecting an agreement between the address signal received at said address terminal and the address stored in said storing means; setting means coupled to said detecting means, for setting an output signal from said detecting means to a predetermined level in accordance with a control signal to override the detecting operation of said detecting means; and inhibiting means coupled between said selecting means and said setting means, for inhibiting the selecting operation of said selecting means in accordance with said predetermined level of said output signal from said detecting means.

Claim 20

A semiconductor memory comprising: a memory array having a plurality of memory cells and a plurality of selecting lines coupled to said memory cells, respectively; a spare memory array having a spare memory cell and a spare selecting line coupled to said spare memory cell; an address terminal means for receiving an address signal; selecting means for selecting one of said selecting lines in accordance with an address signal received at said address terminal means; storing means for storing an address of a known defective memory cell in said memory array; detecting means for detecting an agreement between the address signal received at said address terminal and the address stored in said storing means; setting means coupled to said detecting means, for setting an output signal from said detecting means to a predetermined level in accordance with a control signal to override the detecting operation of said detecting means; and inhibiting means coupled between said selecting means and said setting means, for inhibiting the selecting operation of said selecting means in accordance with said predetermined level of said output signal from said detecting means.

Claim 21

A semiconductor memory according to claim 17, wherein said setting means sets the output signal from said detecting means to said predetermined level when said detecting means detects the agreement so that said defective memory cell is tested.

Claim 22

A semiconductor memory according to claim 18, further comprising a control terminal means for receiving the control signal.

Claim 23

A semiconductor memory according to claim 19, wherein said address storing means comprises a read only memory.

Claim 24

A semiconductor memory according to claim 20, wherein said read only memory comprises a plurality of fuses which are programmed with the known address of a defective memory cell in said memory array in accordance with whether the respective fuses are in an open or closed condition.

Claim 25

A semiconductor memory according to claim 21, wherein said read only memory includes a circuit for cutting said fuses by passing a predetermined current therethrough for programming said read only memory.

Claim 26

A semiconductor memory according to claim 21, wherein said fuses are programmed by laser cutting.