Fabrication process for EEPROMS with high voltage transistors

Claim 2

A fabrication process for EEPROMs with high voltage transistors comprising, forming an N-well in a P-type substrate, implanting an N-type impurity into said substrate in a portion of a memory cell device area and in portions of a high voltage transistor area corresponding to a source and drain thereof, forming a floating gate in said memory device area, forming control gates for N-channel and P-channel devices and for said memory cell and high voltage transistor services, said control gates being formed after said implanting of said N-type impurity, said control gate of said high voltage transistor overlapping said previously formed N-typed impurity implants in said high voltage transistor area, forming additional sources and drains for said devices, said control gates acting as a self-aligning mask, said additional sources and drains including contact sources and drains and drains for said high voltage transistor device overlapping said N-type impurity implants in said high voltage transistor area, and forming one or more layers of conductive lines connecting to selected sources, drains and gates.

Claim 3

The process of claim 1 wherein implanting said N-type impurity comprises implanting arsenic to a dose in the range from 0.5×10 14 /cm 2 to 3.0×10 14 /cm 2 .

Claim 4

The process of claim 1 wherein said high voltage transistor is characterized by a ground-gate breakdown voltage of at least 20 volts.

Claim 5

The process of claim 1 wherein forming said floating gate comprises, thermally growing a first oxide layer on said substrate and opening a window hole therein over said first N-type impurity implant corresponding to said memory cell device, implanting a second N-type impurity in said substrate through said window hole, regrowing a thin oxide layer in said window hole to a thickness of 70-90 Å, depositing a first polysilicon layer over said first oxide layer and said thin oxide layer and selectively removing said first polysilicon layer to form said floating gate disposed over said first oxide layer including said thin-oxide layer, thermally growing a second oxide layer over said floating gate and said substrate, and depositing a second gate layer over said second oxide layer and selectively removing said second gate layer to form said control gates for N-channel and P-channel devices and for said memory cell and high voltage transistor devices.

Claim 6

A fabrication process for EEPROMs with high voltage transistors comprising, forming an N-well in a P-type substrate, defining N-channel, P-channel and memory cell device areas in said substrate, said P-channel device areas being defined in said N-well, said N-channel and P-channel device areas including areas for at least one high-breakdown-voltage transistor, forming N-channel stops and field oxide around said device areas, implanting a first N-type impurity into said substrate in a portion of each memory cell device area and in portions of each high-breakdown-voltage transistor area corresponding to a source and drain thereof, thermally growing a first oxide layer on said substrate and opening a window hole therein over said first N-type impurity implant corresponding to said memory cell device, implanting a second N-type impurity in said substrate through said window hole, regrowing a thin oxide layer in said window hole to a thickness of 70-90 Å, depositing a first polysilicon layer over said first oxide layer and said thin oxide layer, selectively removing said first polysilicon layer and said first oxide layer from all areas of said substrate except said memory cell device areas so as to form a floating gate disposed over said first oxide layer including the thin-oxide window region, thermally growing a second oxide layer over said floating gate and said substrate, introducing a threshold adjusting dopant into selected N-channel and P-channel device areas, depositing a second gate layer over said second oxide layer, selectively removing said second gate layer and said second oxide layer so as to form gates for said N-channel devices, P-channel devices, and memory cell devices, the gates of said high-breakdown-voltage transistors overlapping said first N-type impurity impurity implants corresponding to the sources and drains thereof, forming sources and drains for said devices, said gates acting as a self-aligning mask, said sources and drains including contact sources and drains overlapping said sources and drains of said high-breakdown-voltage transistors, and forming a conductive circuit of lines connecting to selected sources, drains and gates.

Claim 7

A fabrication process for EEPROMs with high voltage transistors comprising, forming an N-well in a P-type substrate, defining N-channel, P-channel and memory cell device areas in said substrate, said P-channel device areas being defined in said N-well, said N-channel and P-channel device areas including areas for at least one high-breakdown-voltage transistor, forming N-channel stops and field oxide around said device areas, implanting a first N-type impurity into said substrate in a portion of each memory cell device area and in portions of each high-breakdown-voltage transistor area corresponding to a source and drain thereof, thermally growing a first oxide layer on said substrate and opening a window hole therein over said first N-type impurity implant corresponding to said memory cell device, implanting a second N-type impurity in said substrate through said window hole, regrowing a thin oxide layer in said window hole to a thickness of 70-90 Å, depositing a first polysilicon layer over said first oxide layer and said thin oxide layer, selectively removing said first polysilicon layer and said first oxide layer from all areas of said substrate except said memory cell device areas so as to form a floating gate disposed over said first oxide layer including the thin-oxide window region, thermally growing a second oxide layer over said floating gate and said substrate, introducing a threshold adjusting dopant into selected N-channel and P-channel device areas, depositing a second gate layer over said second oxide layer, selectively removing said second gate layer and said second oxide layer so as to form gates for said N-channel devices, P-channel devices, and memory cell devices, the gates of said high-breakdown-voltage transistors overlapping said first N-type impurity impurity implants corresponding to the sources and drains thereof, forming sources and drains for said devices, said gates acting as a self-aligning mask, said sources and drains including contact sources and drains overlapping said sources and drains of said high-breakdown-voltage transistors, and forming a conductive circuit of lines connecting to selected sources, drains and gates.

Claim 8

The process of claim 5 wherein forming N-channel stops and field oxide comprises thermally growing a thin silicon dioxide layer with a thickness in the range from 250 to 1000 Å on said substrate, depositing a silicon nitride layer with a thickness in the range from 1000 to 2500 Å on said oxide layer, the thickness ratio of silicon nitride to silicon dioxide being in the range from 1:1 to 7:1, removing said silicon nitride from all areas of said wafer except said device areas, implanting boron ions into said substrate around N-channel device areas and around said N-well, the implantation energy being in the range from 25 to 50 keV, driving in said boron ions and thermally growing oxide in all areas except said device areas covered by said nitride, said driving in step also driving in said first N-type impurity implants, and removing said nitride layer and said thin silicon dioxide layer.

Claim 9

The process of claim 5 wherein implanting said first N-type impurity comprises implanting arsenic to a dose in the range from 0.5×10 14 /cm 2 to 3.0×10 14 /cm 2 .

Claim 10

The process of claim 5 wherein forming said sources and drains comprises implanting phosphorus to a dose in the range from 0.0 to 7.0×10 13 /cm 2 and arsenic to a dose in the range from 1.0×10 15 /cm 2 to 8.0×10 15 /cm 2 in areas of said substrate adjacent to gates of said N-channel devices, and implanting boron to a dose in the range from 1.0×10 15 /cm 2 to 3.0×10 15 /cm 2 in areas of said substrate adjacent to gates of said P-channel devices.

Claim 11

The process of claim 5 wherein said first gate oxide has a thickness in the range from 250 to 750 Å.

Claim 12

The process of claim 5 wherein said at least one high-breakdown-voltage transistor has a grounded gate junction breakdown voltage in a range from 20 to 30 volts.

Claim 13

The process of claim 5 wherein said second gate layer is formed of polysilicon.

Claim 14

The process of claim 5 wherein said second gate layer is formed of a polysilicon/silicide sandwich for high speed operation.

Claim 15

The process of claim 5 wherein the high-breakdown-voltage transistor is formed after field oxidation.