Test method for random defects in electronic microstructures

Claim 1

A method of testing an integrated circuit manufacturing process, which comprises a sequence of unit processes, for defects in a wafer produced by a process, the method comprising the steps of: providing a first and second reticle plates that are spaced apart and substantially parallel; providing a first electronic test pattern on the first reticle plate and a second electronic test pattern on the second reticle plate, with each electronic test pattern comprising a sequence of repeating subpatterns, with each sub-pattern comprising an array of die size patterns and with each die size pattern comprising an array of micro-patterns, where each micropattern on the first reticle plate lies closest to and directly opposite at least one corresponding micro-pattern on the second reticle plate, and where, for a micro-pattern on the first reticle plate and the corresponding micro-pattern on the second reticle plate, at least one of these micro-patterns includes an electrically conductive pattern and an electrical contact pad for activating this electrically conductive pattern; providing an electrically insulating layer of material between the first and second reticle plates; choosing each micro-pattern on the first reticle plate and the corresponding micro-pattern on the second reticle plate to test for the presence of defects in one of the unit processes that comprise the manufacturing process; activating the electrically conductive pattern or patterns for each pair of corresponding micro-patterns on the first and second reticle plates; and identifying the defects in each unit process according to the pairs of corresponding micro-patterns that are found to be inoperative when activated.

Claim 2

A method of testing an integrated circuit manufacturing process, which comprises a sequence of unit processes, for defects in a wafer produced by a process, the method comprising the steps of: providing a first and second reticle plates that are spaced apart and substantially parallel; providing a first electronic test pattern on the first reticle plate and a second electronic test pattern on the second reticle plate, with each electronic test pattern comprising a sequence of repeating subpatterns, with each sub-pattern comprising an array of die size patterns and with each die size pattern comprising an array of micro-patterns, where each micropattern on the first reticle plate lies closest to and directly opposite at least one corresponding micro-pattern on the second reticle plate, and where, for a micro-pattern on the first reticle plate and the corresponding micro-pattern on the second reticle plate, at least one of these micro-patterns includes an electrically conductive pattern and an electrical contact pad for activating this electrically conductive pattern; providing an electrically insulating layer of material between the first and second reticle plates; choosing each micro-pattern on the first reticle plate and the corresponding micro-pattern on the second reticle plate to test for the presence of defects in one of the unit processes that comprise the manufacturing process; activating the electrically conductive pattern or patterns for each pair of corresponding micro-patterns on the first and second reticle plates; and identifying the defects in each unit process according to the pairs of corresponding micro-patterns that are found to be inoperative when activated.

Claim 12

A method of testing unit processes of an integrated circuit manufacturing series for random defects, where the unit processes are used for manufacturing wafers carrying integrated circuits, the method comprising the steps of: (a) simulating multi-level wires of an integrated circuit with electrically conductive first and second layers separated by a dielectric layer, where the conductive layers are established in first and second micro-patterns, respectively; (b) simulating other multi-level conductive first and second layers separated by a dielectric layer, where the conductive layers are established in a plurality of micro-patterns, with the plurality of micro-patterns forming die size patterns within a sub-pattern; (c) providing a test pattern on a wafer by repeating the test patterns over substantially all of the surface of the wafer; (d) fabricating the test pattern in a unit process in a similar manner as a wafer carrying integrated circuits is treated in the unit process; and (e) testing micro-structures formed by the micro-patterns for failure.

Claim 13

A method of testing unit processes of an integrated circuit manufacturing series for random defects, where the unit processes are used for manufacturing wafers carrying integrated circuits, the method comprising the steps of: (a) simulating multi-level wires of an integrated circuit with electrically conductive first and second layers separated by a dielectric layer, where the conductive layers are established in first and second micro-patterns, respectively; (b) simulating other multi-level conductive first and second layers separated by a dielectric layer, where the conductive layers are established in a plurality of micro-patterns, with the plurality of micro-patterns forming die size patterns within a sub-pattern; (c) providing a test pattern on a wafer by repeating the test patterns over substantially all of the surface of the wafer; (d) fabricating the test pattern in a unit process in a similar manner as a wafer carrying integrated circuits is treated in the unit process; and (e) testing micro-structures formed by the micro-patterns for failure.