US4856085A
Expired / Lapsed
US
⏱️ 0.0 years remaining
FM receiver with improved adjacent-channel rejection
Assignee: US Philips Corp
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Filing: 1987-03-23
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Granted: 1989-08-08
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Expires: 2007-03-23
Abstract
Abstract An FM receiver having a phase-locked loop demodulator and a control voltage correction circuit for the local tuning oscillator. The correction circuit includes a comparator for comparing the output frequency of the phase-locked loop demodulator with the output signal from a reference oscillator, the output of the comparator being connected through an integrator to provide a control signal for the local oscillator as part of an automatic frequency control loop. The comparator output is also fed through an integrator to an adder connected between the demodulator output and the demodulator oscillator controlled input, for setting the demodulator oscillator at the center intermediate frequency when no carrier signal is being received.
Inventors
- 👤 Philippe Horvat
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 22:57
CPC Classifications
H; H03; H03D; H03D3/00; H03D3/02; H03D3/24; H03D3/241; H03D3/242
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
193 words
An FM receiver comprising a channel selection and intermediate frequency circuit having a signal output, a phase-locked loop frequency demodulator connected to said signal output and including a demodulator oscillator, and a return path from the demodulator to the channel selection circuit, said return path forming part of a frequency-locked loop for a tuning oscillator of the selection and intermediate frequency circuit, characterized by comprising a voltage correction stage having two outputs, said stage comprising a reference oscillator, at least one integrator, a comparator for comparing signals supplied from said demodulator oscillator with a signal supplied from said reference oscillator, and an adder, said comparator having an output supplied to said at least one integrator, said at least one integrator having an output connected to an input of said tuning oscillator and forming part of said frequency-locked loop for the tuning oscillator, and said at least one integrator having an output connected to said adder, and said adder being connected in said phase-locked loop for adding the output of the demodulator and the output of said at least one integrator, and having an output connected to a control input of said demodulator oscillator.
Claim 2
Dependent Claim
193 words
An FM receiver comprising a channel selection and intermediate frequency circuit having a signal output, a phase-locked loop frequency demodulator connected to said signal output and including a demodulator oscillator, and a return path from the demodulator to the channel selection circuit, said return path forming part of a frequency-locked loop for a tuning oscillator of the selection and intermediate frequency circuit, characterized by comprising a voltage correction stage having two outputs, said stage comprising a reference oscillator, at least one integrator, a comparator for comparing signals supplied from said demodulator oscillator with a signal supplied from said reference oscillator, and an adder, said comparator having an output supplied to said at least one integrator, said at least one integrator having an output connected to an input of said tuning oscillator and forming part of said frequency-locked loop for the tuning oscillator, and said at least one integrator having an output connected to said adder, and said adder being connected in said phase-locked loop for adding the output of the demodulator and the output of said at least one integrator, and having an output connected to a control input of said demodulator oscillator.
Claim 3
Dependent Claim
55 words
A receiver as claimed in claim 1, characterized in that said at least one integrator comprises first and second integrators, each having a respective output, the output of said first integrator being connected to said input of said tuning oscillator, and the output of said second integrator being connected to an input of said adder.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-08-07 | 1993-02-06 | 1993-08-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-08-07 | 1997-02-06 | 1997-08-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-08-07 | 2001-02-06 | 2001-08-08 | $7700.00 | Window Closed / Lapsed |