Semiconductor device

Claim 2

A semiconductor device comprising: (1) an elongated injector region formed in a semiconductor substrate, which has an upper surface and is extended in one direction, said elongated injector region being interposed between first and second surface area of said substrate along said one direction thereof; (2) a plurality of first spaced base regions with collectors therein constituting first IIL gates formed at said first surface area along said one direction of said injector region and closely spaced therefrom; (3) a plurality of second spaced base regions with collectors therein constituting second IIL gates formed at said second surface area along said one direction of said injector region and closely spaced therefrom; (4) first generally parallel conductive layers extending over said substrate and being connected to electrodes of selected ones of said first or second IIL gates; and (5) second generally parallel conductive layers extending in a different direction to said first conductive layers over said substrate and being connected to electrodes of predetermined ones of said first or second IIL gates, wherein said elongated injector is a doped region which is formed by selectively implanting an impurity into said substrate, and wherein at least one of said first conductive layers is formed along and in electrical contact with the whole upper surface of said doped region.

Claim 3

A semiconductor device according to claim 1, wherein a direction of said first conductive layer is substantially parallel to said one direction of said injector region.

Claim 4

A semiconductor device according to claim 1, wherein said first and second conductive layers are substantially perpendicular to each other.

Claim 5

A semiconductor device according to claim 1, wherein said first and second wirings are separate from each other and said substrate by an insulative material, and wherein said second conductive layers connect said electrodes of selected first IIL gates with said electrodes of predetermined second IIL gates at the through holes which are formed said insulative material.

Claim 6

A semiconductor device according to claim 1, wherein the pitch of said first conductive layers is substantially equal to the pitch of the electrodes of one of said first or second IIL gates.

Claim 7

A semiconductor device according to claim 5, wherein the pitch of said second conductive layers is substantially equal to the pitch of said electrodes of first or second IIL gates.

Claim 8

A semiconductor device according to claim 4, wherein said through holes are formed on the electrodes of said first or second IIL gates formed by means of said first conductive layers.

Claim 9

A semiconductor device according to claim 7, wherein the area of the electrodes of said first or second IIL gates exposed through said through holes are substantially equal to or slightly smaller than the area of said electrodes viewed from above.

Claim 10

A semiconductor device according to claim 7, wherein the width of each of said first and second conductive layers in the portion of said through hole is substantially equal to the width of each of said first and second conductive layers in portions other than said portion of said through hole.

Claim 11

A semiconductor device comprising: (1) a plurality of circuit blocks having circuit elements formed in a semiconductor substrate; (2) first generally parallel conductive strips formed over a first insulative material covering said substrate and being connected to selected ones of said circuit elements in each of said circuit blocks; (3) second generally parallel conductive strips formed over a second insulative material covering at least said first conductive strips and being connected to predetermined ones of said circuit elements in each of said circuit blocks, said second conductive strips being arranged substantially perpendicular to said first conductive strip; and (4) third conductive strips disposed over a third insulative material covering at least said second conductive strips and providing electrical connections between (or among) selected ones of said circuit blocks, wherein at least predetermined one of said circuit blocks have first and second IIL gates, wherein the pitch of the first conductive strips is substantially equal to the pitch of the electrodes of one of the first or second IIL gates and the pitch of the second conductive strips is substantially equal to the array pitch of the first or second IIL gates.

Claim 12

A semiconductor device comprising: (1) a plurality of circuit blocks having circuit elements formed in a semiconductor substrate; (2) first generally parallel conductive strips formed over a first insulative material covering said substrate and being connected to selected ones of said circuit elements in each of said circuit blocks; (3) second generally parallel conductive strips formed over a second insulative material covering at least said first conductive strips and being connected to predetermined ones of said circuit elements in each of said circuit blocks, said second conductive strips being arranged substantially perpendicular to said first conductive strip; and (4) third conductive strips disposed over a third insulative material covering at least said second conductive strips and providing electrical connections between (or among) selected ones of said circuit blocks, wherein at least predetermined one of said circuit blocks have first and second IIL gates, wherein the pitch of the first conductive strips is substantially equal to the pitch of the electrodes of one of the first or second IIL gates and the pitch of the second conductive strips is substantially equal to the array pitch of the first or second IIL gates.

Claim 13

A semiconductor device according to claim 10, wherein said selected ones of said circuit blocks includes IIL elements, said IIL elements comprise an elongated injector and gates.

Claim 14

A semiconductor device according to claim 10, wherein said selected ones of said circuit blocks include one block having IIL elements and another block having bipolar elements.

Claim 15

A semiconductor device according to claim 10, wherein said third strips are power wirings for supplying operating voltage to said IIL elements.

Claim 16

A semiconductor device according to claim 11, wherein said third strips are formed over said second insulative material in the extending direction of said first strips formed in contact with said injector.

Claim 17

A semiconductor device according to claim 11, wherein said third strips are formed to be generally parallel with said second strips to electrically connect the electrodes of said gates formed in the areas at opposite ends of said injector.

Claim 18

A semiconductor device comprising: (1) an elongated semiconductor region formed in a semiconductor substrate; (2) a plurality of spaced semiconductor regions facing to but spaced from one elongated side of said elongated semiconductor region; (3) each of said semiconductor regions and said elongated region performing a circuit component function; (4) first elongated conductive members extending over said substrate and being generally parallel to said elongated region; and (5) second elongated conductive members extending over said substrate with a predetermined angle to said first elongated conductive members, wherein selected ones of said first elongated conductive members are connected to predetermined ones of said spaced semiconductor regions and selected ones of said second elongated conductive members are connected to predetermined ones of said first elongated conductive members, and wherein said elongated semiconductor region is a doped region which is formed by selectively implanting an impurity into the substrate, and wherein one of the first conductive members is formed along and in electrical contact with a whole upper surface of the doped region.

Claim 19

A semiconductor device comprising: (1) an elongated semiconductor region formed in a semiconductor substrate; (2) a plurality of spaced semiconductor regions facing to but spaced from one elongated side of said elongated semiconductor region; (3) each of said semiconductor regions and said elongated region performing a circuit component function; (4) first elongated conductive members extending over said substrate and being generally parallel to said elongated region; and (5) second elongated conductive members extending over said substrate with a predetermined angle to said first elongated conductive members, wherein selected ones of said first elongated conductive members are connected to predetermined ones of said spaced semiconductor regions and selected ones of said second elongated conductive members are connected to predetermined ones of said first elongated conductive members, and wherein said elongated semiconductor region is a doped region which is formed by selectively implanting an impurity into the substrate, and wherein one of the first conductive members is formed along and in electrical contact with a whole upper surface of the doped region.

Claim 20

A semiconductor device according to claim 16, wherein said first and second conductive members are formed at different level.

Claim 21

A semiconductor device according to claim 16, wherein said first and second conductive members are substantially perpendicular to each other.

Claim 22

A semiconductor device according to claim 23, wherein said semiconductor regions are formed at the another elongated side of said elongated regions and closely spaced therefrom.

Claim 23

A semiconductor device according to claim 19, wherein said second conductive members extend transversely to said elongated region.

Claim 24

A semiconductor device according to claim 18, wherein said circuit component function is IIL function.

Claim 25

A semiconductor device comprising: (1) an elongated injector region formed in a semiconductor substrate, which has an upper surface and is extended in one direction, said injector region being interposed between first and second surface areas of said substrate along said one direction thereof; (2) a plurality of first spaced base regions with collectors therein constituting first IIL gates formed at said first surface area along said one direction of said injector region and closely spaced therefrom; (3) a plurality of second spaced base regions with collectors therein constituting second IIL gates formed at said second surface area along said one direction of said injector region and closely spaced therefrom; (4) first generally parallel conductive layers extending over said substrate and being connected to electrodes of selected ones of said first or second IIl gates; and (5) second generally parallel conductive layers extending perpendicular to said first conductive layers over said substrate and being connected to electrodes of predetermined ones of said first of second IIL gates, wherein said plurality of first and second spaced base regions are arranged at first predetermined widths (W1) from each other, wherein collectors in said first and second spaced base regions are arranged at second predetermined widths (W2) from each other, and wherein said first generally parallel conductive layers are arranged at said second predetermined widths (W2) and said second generally parallel conductive layers are arranged at a half pitch of said first predetermined widths (W1)×n (1, 2, 3, . . . ).

Claim 26

A semiconductor device comprising: (1) an elongated injector region formed in a semiconductor substrate, which has an upper surface and is extended in one direction, said injector region being interposed between first and second surface areas of said substrate along said one direction thereof; (2) a plurality of first spaced base regions with collectors therein constituting first IIL gates formed at said first surface area along said one direction of said injector region and closely spaced therefrom; (3) a plurality of second spaced base regions with collectors therein constituting second IIL gates formed at said second surface area along said one direction of said injector region and closely spaced therefrom; (4) first generally parallel conductive layers extending over said substrate and being connected to electrodes of selected ones of said first or second IIl gates; and (5) second generally parallel conductive layers extending perpendicular to said first conductive layers over said substrate and being connected to electrodes of predetermined ones of said first of second IIL gates, wherein said plurality of first and second spaced base regions are arranged at first predetermined widths (W1) from each other, wherein collectors in said first and second spaced base regions are arranged at second predetermined widths (W2) from each other, and wherein said first generally parallel conductive layers are arranged at said second predetermined widths (W2) and said second generally parallel conductive layers are arranged at a half pitch of said first predetermined widths (W1)×n (1, 2, 3, . . . ).

Claim 27

A semiconductor device according to claim 22, wherein said elongated injector is a doped region which is formed by selectively implanting an impurity into said substrate, and wherein at least one of said first conductive layers is formed along and in electrical contact with a whole upper surface of said doped region.

Claim 28

A semiconductor device according to claim 22, wherein said first and second generally parallel conductive layers are formed at different levels.

Claim 29

A semiconductor device according to claim 24, wherein said first and second generally parallel conductive layers are separated from each other and said substrate by an insulative material without portions connected to said electrodes.