Monolithic semi-custom IC having standard LSI sections and coupling gate array sections

Claim 2

A monolithic semi-custom system, large scale integration (LSI) circuit comprising: a plurality of different types of standard LSI logic sections, each having a predetermined off-the-shelf logic configuration and wiring pattern; glue circuit means for functionally coupling said standard LSI logic sections, said glue circuit means having a mask design standard suitable for the same manufacturing process conditions as the manufacturing process conditions of said standard LSI logic sections; a wiring region for selectively connecting terminals between said standard LSI logic sections and said glue circuit means; and a bonding pad section surrounding said standard LSI logic sections and said glue circuit means for connecting said terminals to lead wires, wherein said standard LSI logic sections, said glue circuit means, said wiring region and said bonding pad section constitute common hardware as a master, and said standard LSI logic sections, said glue circuit means, said wiring region and said bonding pad section are connected to each other through a selected one or both of single- and multi-layer wiring pattern.

Claim 3

A circuit according to claim 1, wherein said glue circuit means comprises a small scale integration pattern, a medium scale integration pattern and a resistor pattern.

Claim 4

A monolithic semi-custom system, large scale integration circuit (LSI), comprising: a plurality of different types of standard LSI logic sections, each having a predetermined off-the-shelf logic configuration and wiring pattern; at least one gate array block having mask design standards suitable for the same manufacturing process conditions as the manufacturing process conditions of said different types of standard LSI logic sections, and constituting glue circuit means for functionally coupling said different types of standard LSI logic sections; a wiring region for selectively connecting terminals of each of said different types of standard LSI logic sections and terminals of said gate array block; an input/output buffer gate array for an external connection interface, said gate array surrounding said standard LSI logic sections and said gate array block; and a bonding pad section surrounding said input/output buffer gate array for connecting said terminals to lead wires, wherein said standard LSI logic sections, said at least one gate array block, aid wiring region, said input/output buffer gate array and said bonding pad section constitute common hardware as a master, and said standard LSI logic section, said at least one gate array block, said wiring region, said input/output buffer gate array and said bonding pad section are connected through a selected one or both of single- and multi-layer wiring pattern.

Claim 5

A monolithic semi-custom system, large scale integration circuit (LSI), comprising: a plurality of different types of standard LSI logic sections, each having a predetermined off-the-shelf logic configuration and wiring pattern; at least one gate array block having mask design standards suitable for the same manufacturing process conditions as the manufacturing process conditions of said different types of standard LSI logic sections, and constituting glue circuit means for functionally coupling said different types of standard LSI logic sections; a wiring region for selectively connecting terminals of each of said different types of standard LSI logic sections and terminals of said gate array block; an input/output buffer gate array for an external connection interface, said gate array surrounding said standard LSI logic sections and said gate array block; and a bonding pad section surrounding said input/output buffer gate array for connecting said terminals to lead wires, wherein said standard LSI logic sections, said at least one gate array block, aid wiring region, said input/output buffer gate array and said bonding pad section constitute common hardware as a master, and said standard LSI logic section, said at least one gate array block, said wiring region, said input/output buffer gate array and said bonding pad section are connected through a selected one or both of single- and multi-layer wiring pattern.

Claim 6

A monolithic semi-custom system, large scale integration (LSI) circuit, comprising: a plurality of different types of standard LSI logic sections, each having a predetermined off-the-shelf logic configuration and wiring pattern; at least one gate array block having mask design standards suitable for the same manufacturing process conditions as the manufacturing process conditions of said different types of standard LSI logic sections, and constituting glue circuit means for functionally coupling said different types of standard LSI logic sections; a mask read only memory (MROM) which has design standards suitable for the same manufacturing process conditions as those of said different types of standard LSI logic sections and said gate array block, and which is programmed in accordance with a contact hole threshold level write technique so as to operate a desired functional circuit of said standard LSI logic sections and said gate array block; an input/output buffer gate array for an external connection interface, said gate array surrounding said standard LSI logic sections and said gate array block; and a bonding pad section surrounding said input/output buffer gate array for connecting said terminals to lead wires, wherein said standard LSI logic sections, said at least one gate array block, said MROM, said input/output buffer gate array and said bonding pad section constitute common hardware as a master, and said standard LSI logic sections, said at least one gate array block, said MROM, said input/output buffer gate array and said bonding pad section are connected through a selected one both of single- and multi-layer wiring pattern.

Claim 7

A monolithic semi-custom system, large scale integration (LSI) circuit, comprising: a plurality of different types of standard LSI logic sections, each having a predetermined off-the-shelf logic configuration and wiring pattern; at least one gate array block having mask design standards suitable for the same manufacturing process conditions as the manufacturing process conditions of said different types of standard LSI logic sections, and constituting glue circuit means for functionally coupling said different types of standard LSI logic sections; a mask read only memory (MROM) which has design standards suitable for the same manufacturing process conditions as those of said different types of standard LSI logic sections and said gate array block, and which is programmed in accordance with a contact hole threshold level write technique so as to operate a desired functional circuit of said standard LSI logic sections and said gate array block; an input/output buffer gate array for an external connection interface, said gate array surrounding said standard LSI logic sections and said gate array block; and a bonding pad section surrounding said input/output buffer gate array for connecting said terminals to lead wires, wherein said standard LSI logic sections, said at least one gate array block, said MROM, said input/output buffer gate array and said bonding pad section constitute common hardware as a master, and said standard LSI logic sections, said at least one gate array block, said MROM, said input/output buffer gate array and said bonding pad section are connected through a selected one both of single- and multi-layer wiring pattern.