Multilayer wiring technique for a semiconductor device

Claim 1

A method of manufacturing a semiconductor device, comprising the steps of: (a) forming a first conductive pattern on a semiconductor substrate; the first conductive pattern being composed of a material selected from the group consisting of refractory metals, refractory metal silicide and silicon; (b) forming a first interlayer insulating film, covering said first conductive pattern; (c) forming a second conductive pattern, which is composed of a refractory metal and is to be connected to said first conductive pattern and said semiconductor substrate, on said first interlayer insulating film; (d) forming a contact hole reaching said first conductive pattern and said semiconductor substrate through said second conductive pattern and said first interlayer insulating film at a predetermined position; (e) performing an annealing step for gettering planarizing the surface of the insulating film and lowering the resistivity of the first and second conductive patterns, as necessary, at a time different from said step of forming said contact hole; and (f) covering said contact hole with a metal film by selective CVD method, after said annealing step, to connect said second conductive pattern to said first conductive pattern and said semiconductor substrate.

Claim 2

A method of manufacturing a semiconductor device, comprising the steps of: (a) forming a first conductive pattern on a semiconductor substrate; the first conductive pattern being composed of a material selected from the group consisting of refractory metals, refractory metal silicide and silicon; (b) forming a first interlayer insulating film, covering said first conductive pattern; (c) forming a second conductive pattern, which is composed of a refractory metal and is to be connected to said first conductive pattern and said semiconductor substrate, on said first interlayer insulating film; (d) forming a contact hole reaching said first conductive pattern and said semiconductor substrate through said second conductive pattern and said first interlayer insulating film at a predetermined position; (e) performing an annealing step for gettering planarizing the surface of the insulating film and lowering the resistivity of the first and second conductive patterns, as necessary, at a time different from said step of forming said contact hole; and (f) covering said contact hole with a metal film by selective CVD method, after said annealing step, to connect said second conductive pattern to said first conductive pattern and said semiconductor substrate.

Claim 8

A method of manufacturing a semiconductor device, comprising the steps of: (a) forming a first conductive pattern on a semiconductor substrate; the first conductive pattern being composed of a material selected from the group consisting of refractory metals, refractory metal silicide and silicon; (b) forming a first interlayer insulating film, covering said first conductive pattern; (c) forming a second conductive pattern, which is composed of a refractory metal and is to be connected to said first conductive pattern and said semiconductor substrate, on said first interlayer insulating film; (d) forming a second interlayer insulating film, covering said second conductive pattern; (e) forming a contact hole reaching said first conductive pattern and said semiconductor substrate through said second conductive pattern and said first and second interlayer insulating films at a predetermined position; (f) performing an annealing step for gettering, planarizing the surface of the insulating film and lowering the resistivity of the first and second conductive patterns, as necessary, at a time different from said step of forming said contact hole; and (g) covering said contact hole with a metal film by selective CVD method, after said annealing step, to connect said second conductive pattern to said first conductive pattern and said semiconductor substrate; (h) forming a third conductive pattern, connected to said second conductive pattern through said contact hole on said second interlayer insulating film, after said contact hole is covered with the metal film.

Claim 9

A method of manufacturing a semiconductor device, comprising the steps of: (a) forming a first conductive pattern on a semiconductor substrate; the first conductive pattern being composed of a material selected from the group consisting of refractory metals, refractory metal silicide and silicon; (b) forming a first interlayer insulating film, covering said first conductive pattern; (c) forming a second conductive pattern, which is composed of a refractory metal and is to be connected to said first conductive pattern and said semiconductor substrate, on said first interlayer insulating film; (d) forming a second interlayer insulating film, covering said second conductive pattern; (e) forming a contact hole reaching said first conductive pattern and said semiconductor substrate through said second conductive pattern and said first and second interlayer insulating films at a predetermined position; (f) performing an annealing step for gettering, planarizing the surface of the insulating film and lowering the resistivity of the first and second conductive patterns, as necessary, at a time different from said step of forming said contact hole; and (g) covering said contact hole with a metal film by selective CVD method, after said annealing step, to connect said second conductive pattern to said first conductive pattern and said semiconductor substrate; (h) forming a third conductive pattern, connected to said second conductive pattern through said contact hole on said second interlayer insulating film, after said contact hole is covered with the metal film.