US4872161A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Bus circuit for eliminating undesired voltage amplitude
Assignee: Panasonic Holdings Corp
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Filing: 1988-03-21
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Granted: 1989-10-03
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Expires: 2008-03-21
Abstract
Abstract A bus circuit capable of realizing a high speed data transfer cycle by eliminating undesired voltage amplitude of the data bus lines, includes a plurality of data bus lines, a potential initializing circuit for setting the initial potential of these data bus lines, an output port circuit for delivering data to these data bus lines, and an input port circuit for feeding data from these data bus lines. At least one of the data bus lines is a potential sensing line, and the sensing line is coupled to an inverting output circuit for inverting the initial potential from the output port circuit, and the potential change of this inverting output means is detected by a data firm judging means connected to the sensing line, and the output port circuit is deactivated by a control circuit in accordance with a judgement signal from the data firm judging circuit.
Inventors
- 👤 Eisuke Ichinohe
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 03:10
CPC Classifications
H; H04; H04L; H04L12/00; H04L12/28; H04L12/40; H04L12/40006; H04L12/40045
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
187 words
A bus circuit comprising: a plurality of data bus lines and at least one sensing line; a potential initializing means for setting an initial potential of said plurality of data bus lines and said sensing line; an output port circuit for supplying data to said plurality of data bus lines upon receiving an output control signal; a discharging means for discharging said sensing line upon receiving said output control signal; an input port circuit for receiving data from said plurality of data bus lines; a data firm judging circuit coupled to said sensing line for detecting a potential change of said sensing line and for generating a judgement signal, said data firm judging circuit including: an inverter circuit for detection of a threshold voltage of said sensing line, a delay means for delaying an output of said inverter circuit, and a NOR circuit for receiving an output of said delay circuit and said output of said inverter circuit, wherein said judgement signal is generated at said output of said NOR circuit; and, a control means for deactivating said output port circuit in response to said judgement signal.
Claim 2
Dependent Claim
187 words
A bus circuit comprising: a plurality of data bus lines and at least one sensing line; a potential initializing means for setting an initial potential of said plurality of data bus lines and said sensing line; an output port circuit for supplying data to said plurality of data bus lines upon receiving an output control signal; a discharging means for discharging said sensing line upon receiving said output control signal; an input port circuit for receiving data from said plurality of data bus lines; a data firm judging circuit coupled to said sensing line for detecting a potential change of said sensing line and for generating a judgement signal, said data firm judging circuit including: an inverter circuit for detection of a threshold voltage of said sensing line, a delay means for delaying an output of said inverter circuit, and a NOR circuit for receiving an output of said delay circuit and said output of said inverter circuit, wherein said judgement signal is generated at said output of said NOR circuit; and, a control means for deactivating said output port circuit in response to said judgement signal.
Claim 3
Dependent Claim
196 words
A bus circuit comprising: a plurality of data bus lines; a potential initializing means for setting an initial potential of said plurality of data bus lines upon receiving a precharge control signal; an output port circuit for supplying data to said plurality of data bus lines upon receiving an output control signal; an input port circuit for receiving data from said plurality of data bus lines; a data firm judging circuit coupled to each of said data bus lines for detecting a potential change of at least one of said data bus lines and for generating a judgement signal, said data firm judging circuit including: inverter circuits coupled to each of said data bus lines for detection of a threshold voltage, an OR circuit having as inputs said inverter circuits, a delay means for delaying an output of said OR circuit, and a NOR circuit having as inputs and output of said delay means and said output of said OR circuit, wherein said judgement signal is generated at an output of said NOR circuit; and, a control means for deactivating said output port circuit in accordance with said judgement signal from said data firm judging circuit.
Claim 4
Dependent Claim
196 words
A bus circuit comprising: a plurality of data bus lines; a potential initializing means for setting an initial potential of said plurality of data bus lines upon receiving a precharge control signal; an output port circuit for supplying data to said plurality of data bus lines upon receiving an output control signal; an input port circuit for receiving data from said plurality of data bus lines; a data firm judging circuit coupled to each of said data bus lines for detecting a potential change of at least one of said data bus lines and for generating a judgement signal, said data firm judging circuit including: inverter circuits coupled to each of said data bus lines for detection of a threshold voltage, an OR circuit having as inputs said inverter circuits, a delay means for delaying an output of said OR circuit, and a NOR circuit having as inputs and output of said delay means and said output of said OR circuit, wherein said judgement signal is generated at an output of said NOR circuit; and, a control means for deactivating said output port circuit in accordance with said judgement signal from said data firm judging circuit.
Claim 5
Dependent Claim
166 words
A bus circuit comprising: a plurality of data bus lines and at least one sensing lines; a potential initializing means for setting an initial potential of said plurality of data bus lines and said sensing line upon receiving a precharge control signal; an output port circuit for supplying data to said plurality of data bus lines upon receiving an output control signal; a discharging means for discharging said sensing line upon receiving said ouput control signal; an input port circuit for receiving data from said plurality of data bus lines, a data firm judging circuit coupled to said sensing line for detecting a potential change of said sensing line and for producing a judgement signal; a control means for deactivating said output port circuit in accordance with judgement signal from said data firm judging circuit, and for activating said potential initializing means to precharge said plurality of data bus lines and said sensing line in accordance with said judgement signal from said data firm judging circuit.
Claim 6
Dependent Claim
166 words
A bus circuit comprising: a plurality of data bus lines and at least one sensing lines; a potential initializing means for setting an initial potential of said plurality of data bus lines and said sensing line upon receiving a precharge control signal; an output port circuit for supplying data to said plurality of data bus lines upon receiving an output control signal; a discharging means for discharging said sensing line upon receiving said ouput control signal; an input port circuit for receiving data from said plurality of data bus lines, a data firm judging circuit coupled to said sensing line for detecting a potential change of said sensing line and for producing a judgement signal; a control means for deactivating said output port circuit in accordance with judgement signal from said data firm judging circuit, and for activating said potential initializing means to precharge said plurality of data bus lines and said sensing line in accordance with said judgement signal from said data firm judging circuit.
Claim 7
Dependent Claim
148 words
A bus circuit comprising: a plurality of data bus lines; a potential initializing means for setting an initial potential of said plurality of data bus lines upon receiving a precharge control signal; an output port circuit for supplying data to said plurality of data bus lines upon receiving an output control signal; an input port circuit for receiving data from said plurality of data bus lines; a data firm judging circuit coupled to said data bus lines for detecting a potential change of at least one of said data bus lines and for producing a judgement signal; a control means for deactivating said output port circuit in accordance with judgement signal from said data firm judging circuit, and for activating said potential initializing means to precharge said plurality of data bus lines and said sensing line in accordance with said judgment signal from said data firm judging circuit.
Claim 8
Dependent Claim
148 words
A bus circuit comprising: a plurality of data bus lines; a potential initializing means for setting an initial potential of said plurality of data bus lines upon receiving a precharge control signal; an output port circuit for supplying data to said plurality of data bus lines upon receiving an output control signal; an input port circuit for receiving data from said plurality of data bus lines; a data firm judging circuit coupled to said data bus lines for detecting a potential change of at least one of said data bus lines and for producing a judgement signal; a control means for deactivating said output port circuit in accordance with judgement signal from said data firm judging circuit, and for activating said potential initializing means to precharge said plurality of data bus lines and said sensing line in accordance with said judgment signal from said data firm judging circuit.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-10-02 | 1993-04-03 | 1993-10-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-10-02 | 1997-04-03 | 1997-10-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-10-02 | 2001-04-03 | 2001-10-03 | $7700.00 | Window Closed / Lapsed |