US4873672A
Expired / Lapsed
US
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Dynamic random access memory capable of fast erasing of storage data
Assignee: Micron Memory Japan Ltd
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Filing: 1987-05-20
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Granted: 1989-10-10
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Expires: 2007-05-20
Abstract
Abstract This invention relates to a semiconductor memory having a high speed operation and a high integration density. When a high integration semiconductor memory is applied to a large scale computer system, storage data must be erased at a high speed for data security. The present invention erases the storage data by a method which is different from the write method of conventional prior art. In the invention, the erasing operation is made by continuously selecting word lines while sense amplifiers are kept in this on-state. The present invention includes a control circuit for attaining such an operation, and can be used for a semiconductor memory implemented in a computer system accessed by a plurality of users.
Inventors
- 👤 Jun Etoh
- 👤 Katsuhiro Shimohigashi
- 👤 Kazuyuki Miyazawa
- 👤 Katsutaka Kimura
- 👤 Takesada Akiba
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 18:54
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C11/4078; G11C11/4072
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
222 words
A semiconductor dynamic random access memory comprising: a plurality of word lines; a plurality of data lines arranged in such a manner as to cross said word lines; memory cells electrically connected to said word lines and to said data lines; sense amplification circuits coupled to said data lines, respectively; selection means for selecting one of said word lines; means for selecting one of said data lines; means for writing predetermined data into said memory cells by use of said data lines; means for providing a control signal for controlling an operation of erasing storage data stored in the memory cells; means for precharging said data lines; means for sequentially selecting and driving said word lines responding to the control signal while the storage data is erased; and control circuit means for holding said sense amplification circuits under an on-state responding to the control signal while said word lines are sequentially selected and driven, while the storage data is erased, wherein said control circuit means comprises: a data line precharge signal control circuit for controlling said precharge means to be in an off-state while the storage data is erased, responding to the control signal; and a sense amplifier control circuit for controlling the sense amplification circuits to be in their on-states while the storage data is erased, responding to the control signal.
Claim 2
Dependent Claim
222 words
A semiconductor dynamic random access memory comprising: a plurality of word lines; a plurality of data lines arranged in such a manner as to cross said word lines; memory cells electrically connected to said word lines and to said data lines; sense amplification circuits coupled to said data lines, respectively; selection means for selecting one of said word lines; means for selecting one of said data lines; means for writing predetermined data into said memory cells by use of said data lines; means for providing a control signal for controlling an operation of erasing storage data stored in the memory cells; means for precharging said data lines; means for sequentially selecting and driving said word lines responding to the control signal while the storage data is erased; and control circuit means for holding said sense amplification circuits under an on-state responding to the control signal while said word lines are sequentially selected and driven, while the storage data is erased, wherein said control circuit means comprises: a data line precharge signal control circuit for controlling said precharge means to be in an off-state while the storage data is erased, responding to the control signal; and a sense amplifier control circuit for controlling the sense amplification circuits to be in their on-states while the storage data is erased, responding to the control signal.
Claim 3
Dependent Claim
31 words
A semiconductor memory according to claim 1, further comprising: means for simultaneously selecting predetermined ones of said data lines; and means for simultaneously writing predetermined data into said selected data lines.
Claim 4
Dependent Claim
23 words
A semiconductor memory according to claim 1, further comprising means for holding the predetermined while said word lines are sequentially selected and driven.
Claim 5
Dependent Claim
29 words
A semiconductor dynamic random access memory according to claim 1, wherein said precharging means comprises a plurality of precharging circuits respectively coupled to predetermined pairs of said data lines.
Claim 6
Dependent Claim
27 words
A semiconductor dynamic random access memory according to claim 1, wherein each of said sense amplifier circuits is respectively coupled to a pair of said data lines.
Claim 7
Dependent Claim
243 words
A semiconductor dynamic random access memory comprising a plurality of memory arrays, each of which comprises: a plurality of word lines; a plurality of data lines arranged in such a manner as to cross said word lines; memory cells electrically connected to said word lines and to said data lines; sense amplification circuits coupled to said data lines, respectively; a plurality of common data lines electrically connected to said data lines; selection means for selecting one of said word lines; means for selecting one of said data lines; means for writing predetermined data into said memory cells by use of said data lines; means for providing a control signal for controlling an operation of erasing storage data stored in the memory cells; means for precharging said data lines; means for sequentially selecting and driving said word lines responding to the control signal while the storage data is erased; and control circuit means for holding said sense amplification circuits under an on-state responding to the control signal while said word lines are sequentially selected and driven, while the storage data is erased, wherein said control circuit means comprises: a data line precharge signal control circuit for controlling said precharge means to be in an off-state while the storage data is erased, responding to the control signal; and a sense amplifier control circuit for controlling the sense amplification circuits to be in their on-states while the storage data is erased, responding to the control signal.
Claim 8
Dependent Claim
243 words
A semiconductor dynamic random access memory comprising a plurality of memory arrays, each of which comprises: a plurality of word lines; a plurality of data lines arranged in such a manner as to cross said word lines; memory cells electrically connected to said word lines and to said data lines; sense amplification circuits coupled to said data lines, respectively; a plurality of common data lines electrically connected to said data lines; selection means for selecting one of said word lines; means for selecting one of said data lines; means for writing predetermined data into said memory cells by use of said data lines; means for providing a control signal for controlling an operation of erasing storage data stored in the memory cells; means for precharging said data lines; means for sequentially selecting and driving said word lines responding to the control signal while the storage data is erased; and control circuit means for holding said sense amplification circuits under an on-state responding to the control signal while said word lines are sequentially selected and driven, while the storage data is erased, wherein said control circuit means comprises: a data line precharge signal control circuit for controlling said precharge means to be in an off-state while the storage data is erased, responding to the control signal; and a sense amplifier control circuit for controlling the sense amplification circuits to be in their on-states while the storage data is erased, responding to the control signal.
Claim 9
Dependent Claim
31 words
A semiconductor memory according to claim 6, further comprising: means for simultaneously selecting predetermined ones of said data lines; and means for simultaneously writing predetermined data into said selected data lines.
Claim 10
Dependent Claim
24 words
A semiconductor memory according to claim 6, further comprising means for holding the predetermined data while said word lines are sequentially selected and driven.
Claim 11
Dependent Claim
29 words
A semiconductor dynamic random access memory according to claim 6, wherein said precharging means comprises a plurality of precharging circuits respectively coupled to predetermined pairs of said data lines.
Claim 12
Dependent Claim
27 words
A semiconductor dynamic random access memory according to claim 6, wherein each of said sense amplifier circuits is respectively coupled to a pair of said data lines.
Claim 13
Dependent Claim
224 words
A semiconductor dynamic random access memory comprising: a plurality of word lines; a plurality of data lines arranged in such a manner as to cross said word lines; memory cells electrically connected to said word lines and to said data lines; sense amplification circuits coupled to said data lines, respectively; selection means for selecting one of said word lines; means for selecting at least two of said data lines; means for writing predetermined data into said memory cells by use of said data lines; means for providing a control signal for controlling an operation of erasing storage data stored in the memory cells; means for precharging said data lines; means for sequentially selecting and driving said word lines responding to the control signal while the storage data is erased; and control circuit means for holding said sense amplification circuits under an on-state responding to the control signal while said word lines are sequentially selected and driven while the storage data is erased, wherein said control circuit means comprises: a data line precharge signal control circuit for controlling the precharge means to be in an off-state while the storage data is erased, responding to the control signal; and a sense amplifier control circuit for controlling the sense amplification circuits to be in their on-states while the storage data is erased, responding to the control signal.
Claim 14
Dependent Claim
224 words
A semiconductor dynamic random access memory comprising: a plurality of word lines; a plurality of data lines arranged in such a manner as to cross said word lines; memory cells electrically connected to said word lines and to said data lines; sense amplification circuits coupled to said data lines, respectively; selection means for selecting one of said word lines; means for selecting at least two of said data lines; means for writing predetermined data into said memory cells by use of said data lines; means for providing a control signal for controlling an operation of erasing storage data stored in the memory cells; means for precharging said data lines; means for sequentially selecting and driving said word lines responding to the control signal while the storage data is erased; and control circuit means for holding said sense amplification circuits under an on-state responding to the control signal while said word lines are sequentially selected and driven while the storage data is erased, wherein said control circuit means comprises: a data line precharge signal control circuit for controlling the precharge means to be in an off-state while the storage data is erased, responding to the control signal; and a sense amplifier control circuit for controlling the sense amplification circuits to be in their on-states while the storage data is erased, responding to the control signal.
Claim 15
Dependent Claim
31 words
A semiconductor memory according to claim 11, further comprising: means for simultaneously selecting predetermined ones of said data lines; and means for simultaneously writing predetermined data into said selected data lines.
Claim 16
Dependent Claim
24 words
A semiconductor memory according to claim 11, further comprising means for holding the predetermined data while said word lines are sequentially selected and driven.
Claim 17
Dependent Claim
29 words
A semiconductor dynamic random access memory according to claim 11, wherein said precharging mean comprises a plurality of precharging circuits respectively coupled to predetermined pairs of said data lines.
Claim 18
Dependent Claim
27 words
A semiconductor dynamic random access memory according to claim 11, wherein each of said sense amplifier circuits is respectively coupled to a pair of said data lines.
References Cited (Backward Citations)
US4758990A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-10-09 | 1993-04-10 | 1993-10-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-10-09 | 1997-04-10 | 1997-10-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-10-09 | 2001-04-10 | 2001-10-10 | $7700.00 | Window Closed / Lapsed |