Driver circuit having a current mirror circuit

Claim 2

A driver circuit characterized by including at least one current mirror circuit which is controlled by a pulse input signal and an output current of which drives a load, wherein said current mirror circuit includes a first MOS transistor and a second MOS transistor, the sources of said first MOS transistor and said second MOS transistor being supplied with an operating potential, the drain of said first MOS transistor being connected electrically to said load to be driven by said output current, the gate and the drain of said second MOS transistor being electrically connected to a current source, and the gate of said first MOS transistor and the gate of said second MOS transistor being connected electrically to one another through first means which is controlled by said pulse signal.

Claim 3

A driver circuit according to claim 1, wherein the output voltage of said load is compared with a predetermined reference voltage by a comparator, and said current mirror circuit is controlled by an output signal of said comparator.

Claim 4

A driver circuit according to claim 1, wherein the source of said first MOS transistor is connected electrically to a voltage limiter circuit.

Claim 5

A driver circuit according to claim 1, wherein said load exists outside a semiconductor chip in which said driver circuit is disposed.

Claim 6

A driver circuit according to claim 1, which further comprises a discharge circuit which includes at least another current mirror circuit controlled by said pulse input signal and which discharges said load by an output current of said other current mirror circuit.

Claim 7

A driver circuit according to claim 1, which further comprises voltage reduction means disposed between the source of said second MOS transistor and said operating potential.

Claim 8

A driver circuit according to claim 1, wherein said current source includes control means for controlling a current value of said current based on a change in at least one of the values of the operating potential, and a channel length and a threshold voltage of said first and second MOS transistors.

Claim 9

A driver circuit according to claim 7, wherein said control of said current value is made in such a manner that the current of said current source is increased when said channel length is great or when said threshold voltage is high, and is reduced when said channel length is small or said threshold voltage is low.

Claim 10

A dynamic random access memory comprising: a word line; a plurality of data line pairs disposed in such a manner as to intersect said word line; dynamic memory cells disposed at the intersections between said word line and said plurality of data line pairs, wherein each of said dynamic memory cells includes a MOS transistor connected at its gate electrode to said word line, and a capacitor connected at one electrode thereof to a corresponding data line through a drain-source path of said MOS transistor; a plurality of sense amplifier means each of which is coupled to each pair of said plurality of data line pairs, wherein each of said plurality of sense amplifier means includes a first p-channel MOS transistor and a second p-channel MOS transistors, wherein the sources of said first and said second p-channel MOS transistors are commonly connected, wherein the drain of said first p-channel MOS transistor and the gate of said second p-channel MOS transistor are coupled to one line of said each pair, and wherein the drain of said second p-channel MOS transistor and the gate of said first p-channel MOS transistor are coupled to another line of said each pair; and a driver circuit, an output current of which drives said sources of said first and said second p-channel MOS transistors of said plurality of sense amplifier means in response to a pulse input signal, wherein said driver circuit includes a current mirror circuit which is controlled by said pulse input signal, and wherein said current mirror circuit includes a first MOS transistor and a second MOS transistor, wherein the sources of said first MOS transistor and said second MOS transistor are supplied with an operating potential, wherein the drain of said first MOS transistor is connected electrically to said sources of said first and said second p-channel MOS transistors of said plurality of sense amplifier means, wherein the gate and the drain of said second MOS transistor are connected electrically to a current source, and wherein the gate of said first MOS transistor and the gate of said second MOS transistor are connected electrically to one another through first means which is controlled by said pulse signal.

Claim 11

A dynamic random access memory comprising: a word line; a plurality of data line pairs disposed in such a manner as to intersect said word line; dynamic memory cells disposed at the intersections between said word line and said plurality of data line pairs, wherein each of said dynamic memory cells includes a MOS transistor connected at its gate electrode to said word line, and a capacitor connected at one electrode thereof to a corresponding data line through a drain-source path of said MOS transistor; a plurality of sense amplifier means each of which is coupled to each pair of said plurality of data line pairs, wherein each of said plurality of sense amplifier means includes a first p-channel MOS transistor and a second p-channel MOS transistors, wherein the sources of said first and said second p-channel MOS transistors are commonly connected, wherein the drain of said first p-channel MOS transistor and the gate of said second p-channel MOS transistor are coupled to one line of said each pair, and wherein the drain of said second p-channel MOS transistor and the gate of said first p-channel MOS transistor are coupled to another line of said each pair; and a driver circuit, an output current of which drives said sources of said first and said second p-channel MOS transistors of said plurality of sense amplifier means in response to a pulse input signal, wherein said driver circuit includes a current mirror circuit which is controlled by said pulse input signal, and wherein said current mirror circuit includes a first MOS transistor and a second MOS transistor, wherein the sources of said first MOS transistor and said second MOS transistor are supplied with an operating potential, wherein the drain of said first MOS transistor is connected electrically to said sources of said first and said second p-channel MOS transistors of said plurality of sense amplifier means, wherein the gate and the drain of said second MOS transistor are connected electrically to a current source, and wherein the gate of said first MOS transistor and the gate of said second MOS transistor are connected electrically to one another through first means which is controlled by said pulse signal.

Claim 12

A dynamic random access memory according to claim 9, wherein a voltage at said sources of said first and said second p-channel MOS transistors of said plurality of sense amplifier means is compared with a predetermined reference voltage by a comparator, and said current mirror circuit is controlled by an output signal of said comparator.

Claim 13

A dynamic random access memory according to claim 9, wherein said source of said first MOS transistor of said current mirror circuit in said driver circuit is connected electrically to a voltage limiter circuit.