Failure information processing in automatic memory tester

Claim 1

Automatic memory tester apparatus for processing failure information of a memory under test (MUT) having plural memory elements and associated MUT addresses, said apparatus comprising a high speed pattern generator for providing digital test patterns to said MUT for storage of data at said MUT addresses in said MUT, a failure processor for comparing outputs from said MUT with expected outputs to obtain failure information, a fail map random access memory (RAM) having fail map addresses corresponding to said MUT addresses and connected to receive said failure information and store it at corresponding said fail map addresses, said fail map addresses including bits to address individual bits of multibit words, address circuitry means for randomly addressing and reading individual bits of said multibit words to provide a serial bit output in which individual bits are in a different sequence than the sequence in which they are stored in said fail map RAM, said different sequence relating to relative topical positions of said memory elements corresponding to individual bits of said serial bit sequences, said address circuitry means including an address generator of said high-speed pattern generator connected to address said fail map RAM, and means for receiving said serial bit output and visually displaying failure information in a two-dimensional display in which relative positions of display of said individual bits relate to topical positions of associated memory elements on said MUT.