Patent US2704049A successfully refreshed from Google Patents.
US4878100A
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US
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Triple-implanted drain in transistor made by oxide sidewall-spacer method
Assignee: Texas Instruments Inc
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Filing: 1989-02-23
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Granted: 1989-10-31
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Expires: 2009-02-23
Abstract
Abstract A transistor for VLSI devices made by the sidewall-spacer method uses a reach-through implant both before and after the sidewall spacer is defined. An arsenic implant self-aligned with the gate prior to the sidewall oxide, then a phosphorus implant and lateral diffusion performed after the sidewall oxide etch creates a reduced impurity concentration and graded junction for the reach-through implanted region beneath the oxide sidewall spacer. An arsenic implant after the sidewall spacer is in place provides heavily-doped low-resistance source/drain regions.
Inventors
- 👤 James M. McDavid
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 10:06
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/0223; H10D30/0227; H10D30/60; H10D30/601; H10D30/603; H10D30/605; Y; Y10; Y10S; Y10S257/00; Y10S257/90
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
103 words
A field-effect transistor comprising a gate on a face of a semiconductor body, a channel beneath the gate, a heavily-doped drain region in said face spaced from the channel, first and second lightly-doped regions in the gap between the drain region and the channel, and a sidewall-spacer oxide segment above said gap, the impurity in said heavily-doped region being at a much higher doping level and diffused into the semiconductor body to a much lesser extent than the impurity in said lightly-doped regions, the impurities of the first and second regions being of differing diffusion coefficient and doping level providing a graded junction.
Claim 2
Dependent Claim
103 words
A field-effect transistor comprising a gate on a face of a semiconductor body, a channel beneath the gate, a heavily-doped drain region in said face spaced from the channel, first and second lightly-doped regions in the gap between the drain region and the channel, and a sidewall-spacer oxide segment above said gap, the impurity in said heavily-doped region being at a much higher doping level and diffused into the semiconductor body to a much lesser extent than the impurity in said lightly-doped regions, the impurities of the first and second regions being of differing diffusion coefficient and doping level providing a graded junction.
Claim 3
Dependent Claim
39 words
A device according to claim 1 in which the semiconductor body is P type silicon, the impurity in the heavily-doped region is arsenic, and the impurity in the lightly-doped regions are arsenic and phosphorous, to provide an N-channel transistor.
References Cited (Backward Citations)
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-10-30 | 1993-05-01 | 1993-10-31 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-10-30 | 1997-05-01 | 1997-10-31 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-10-30 | 2001-05-01 | 2001-10-31 | $7700.00 | Window Closed / Lapsed |