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US4884120A Expired / Lapsed US ⏱️ 0.0 years remaining

Semiconductor device and method for making the same

Assignee: Mitsubishi Electric Corp
•
Filing: 1987-02-20
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Granted: 1989-11-28
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Expires: 2007-02-20
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Abstract

Abstract An improved interconnection structure and method for forming the interconnection in a semiconductor device having multilayered interconnection structure in which a contact hole for electrically connecting a first layer interconnection to a predetermined region of a semiconductor substrate and a through hole for electrically connecting a second layer interconnection to the first layer interconnection are formed in the regions overlapping with each other in planer layout. In the interconnection structure of the present invention, hillocks effective to compensate for the contact hole step are formed in the first layer interconnection only in the region of the contact hole of the first layer interconnection. In the method for forming the interconnection according to the present invention, a first layer interconnection is formed and a chemical conversion process is selectively performed to form a film which is more rigid than the first layer interconnection film on a predetermined region of the first layer interconnection film, and then a heat process is performed to generate hillocks only at the region of the contact hole of the first layer interconnection film. The second layer interconnection film is formed thereafter.

Inventors

  • 👤 Hiroshi Mochizuki
  • 👤 Reiji Tamaki
  • 👤 Junichi Arima
  • 👤 Masaaki Ikegami
  • 👤 Eisuke Tanaka
  • 👤 Kenji Saito

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-07 15:03
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/01; H10W20/031; H10W20/056; H10P; H10P14/00; H10P14/60; H10P14/63; H10P14/6302; H10P14/6304; H10P14/6314; H10W20/032; H10W20/038; H10W20/062; H10W20/064; H10W20/065; H10W20/071; H10W20/081; H10W20/089

Claims Analysis

Total Claims: 5
Claim 1
Independent Claim 191 words
A semiconductor device comprising: a semiconductor substrate; a first insulating film formed on a surface of said semiconductor substrate and having, in a predetermined region thereof, a first penetrating hole reaching the surface of said semiconductor substrate; a first interconnection film formed on a predetermined region of said first insulating film and electrically connected to the surface of said semiconductor substrate via said first penetrating hole; an encapsulation layer, comprising an oxide of said first interconnection film, formed on said first interconnection layer and on said first insulation film, said encapsulation layer having a void therethrough overlapping said first penetrating hole; a second insulating film formed on said encapsulation layer and said first insulating film and having in that region which overlaps with said first penetrating hole in planar layout a second penetrating hole reaching the surface of said first interconnection film; and a second interconnection film formed on a predetermined region of said second insulating film and electrically connected to said first interconnection film via said second penetrating hole, wherein said first interconnection film has a hillock selectively formed at said first penetrating hole portion and having a predetermined height.
Claim 2
Dependent Claim 191 words
A semiconductor device comprising: a semiconductor substrate; a first insulating film formed on a surface of said semiconductor substrate and having, in a predetermined region thereof, a first penetrating hole reaching the surface of said semiconductor substrate; a first interconnection film formed on a predetermined region of said first insulating film and electrically connected to the surface of said semiconductor substrate via said first penetrating hole; an encapsulation layer, comprising an oxide of said first interconnection film, formed on said first interconnection layer and on said first insulation film, said encapsulation layer having a void therethrough overlapping said first penetrating hole; a second insulating film formed on said encapsulation layer and said first insulating film and having in that region which overlaps with said first penetrating hole in planar layout a second penetrating hole reaching the surface of said first interconnection film; and a second interconnection film formed on a predetermined region of said second insulating film and electrically connected to said first interconnection film via said second penetrating hole, wherein said first interconnection film has a hillock selectively formed at said first penetrating hole portion and having a predetermined height.
Claim 3
Dependent Claim 36 words
A semiconductor device according to claim 1, wherein said hillock is formed by subjecting said first interconnection film to a boiling process and to a heat process to cause said interconnection film to form said hillock.
Claim 4
Dependent Claim 17 words
A semiconductor device according to claim 2, wherein said boiling process is carried out in deionized water.
Claim 5
Dependent Claim 21 words
A semiconductor device according to claim 1, wherein said first interconnection film is an aluminum film or an aluminum alloy film.

References Cited (Backward Citations)

US3866311A Cited
DE3109801A1 Cited
GB2128025A Cited
US4698125A Cited
US4734754A Cited
JPS61280638A Cited
EP0216017A2 Cited
US4707457A Cited
JPH064258A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1992-11-27 1993-05-29 1993-11-28 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1996-11-27 1997-05-29 1997-11-28 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2000-11-27 2001-05-29 2001-11-28 $7700.00 Window Closed / Lapsed

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