US4884195A
Expired / Lapsed
US
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Multiprocessor system for loading microprograms into a RAM control store of a bus controller
Assignee: Hitachi Ltd
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Filing: 1986-08-11
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Granted: 1989-11-28
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Expires: 2006-08-11
Abstract
Abstract In a multiprocessor system having a plurality of independent modules including a processor and a memory where the modules are connected via a common transmission path, a transmission control section for handling the interface with the transmission path between the modules is also equipped with a dedicated processor and controlled by its own microprogram. In accordance with the present invention, the memory for storing the microprogam therein is constituted by a writable memory, and the system is so configured that the microprogram may be loaded not only from the inside of the concerned module but also from another module through the common transmission path. Since the microprogram of the transmission control section can thus be loaded from two routes, the system can be configured or reconfigured with significant flexibility.
Inventors
- 👤 Norikazu Endo
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 13:55
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/44; G06F9/4401; G06F9/4403; G06F15/00; G06F15/16; G06F15/177; G06F9/22; G06F9/24
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
292 words
A multiprocessor system including: at least two modules wherein each module includes, (a) a first processor for executing arithmetic processing and peripheral control, (b) a first memory for storing program and data wherein said program and data controls said first processor, (c) an input-output controller controlled by said first processor wherein said input-output controller controls external input-output devices, (d) a transmission controller controlled by said first processor wherein said transmission controller controls information transfers from/to another module, and (e) a first common transmission path connected to said first processor, said first memory, said input-output controller and said transmission controller for permitting information transfers between said first processor, said first memory, said input-output controller and said transmission controller; and a second common transmission path respectively connected to transmission controllers of said modules for permitting information transfers between said modules via said transmission controllers, said transmission controller includes a second processor for executing arithmetic processing, a second memory for storing microgprogram wherein said microprogram controls said second processor, said second memory being writable, a first circuit connected to said first common transmission path and said second memory, said first circuit being controlled, in an initial state following a power-on sequence, by said first processor such that microprogram, transferred through said first transmission path, is stored in said second memory, a second circuit connected to said second common transmission path and said second memory, said second circuit stores microprogram, transferred through said second transmission path subsequent to recognizing an identification code of an associated module, in said second memory during a power-on sequence, and means connected to said first circuit, said second circuit and said second memory for sending said microprogram obtained from either said first circuit or said second circuit to said second memory.
Claim 2
Dependent Claim
292 words
A multiprocessor system including: at least two modules wherein each module includes, (a) a first processor for executing arithmetic processing and peripheral control, (b) a first memory for storing program and data wherein said program and data controls said first processor, (c) an input-output controller controlled by said first processor wherein said input-output controller controls external input-output devices, (d) a transmission controller controlled by said first processor wherein said transmission controller controls information transfers from/to another module, and (e) a first common transmission path connected to said first processor, said first memory, said input-output controller and said transmission controller for permitting information transfers between said first processor, said first memory, said input-output controller and said transmission controller; and a second common transmission path respectively connected to transmission controllers of said modules for permitting information transfers between said modules via said transmission controllers, said transmission controller includes a second processor for executing arithmetic processing, a second memory for storing microgprogram wherein said microprogram controls said second processor, said second memory being writable, a first circuit connected to said first common transmission path and said second memory, said first circuit being controlled, in an initial state following a power-on sequence, by said first processor such that microprogram, transferred through said first transmission path, is stored in said second memory, a second circuit connected to said second common transmission path and said second memory, said second circuit stores microprogram, transferred through said second transmission path subsequent to recognizing an identification code of an associated module, in said second memory during a power-on sequence, and means connected to said first circuit, said second circuit and said second memory for sending said microprogram obtained from either said first circuit or said second circuit to said second memory.
Claim 3
Independent Claim
320 words
A method for loading a microprogram in a second memory of a multiprocessor system including at least first and second modules each having, (a) a first processor for executing arithmetic processing and peripheral control, (b) a first memory for storing program and data wherein said program and data controls said first processor, (c) an input-output controller controlled by said controls external input-output devices, (d) a transmission controller controlled by said first processor wherein said transmission controller controls information transfers from/to another module, said transmission controller including a second processor for executing arithmetic processing and a second writable memory for storing microprogram wherein said microprogram controls said second processor, (e) a first common transmission path connected to said first processor, said first memory, said input-output controller and said transmission controller for permitting information transfers between said first processor, said first memory, said input-output controller and said transmission controller; and a second common transmission path respectively connected to transmission controllers of said modules for permitting information transfers between said first and second modules via said transmission controllers, said method comprising the steps of: storing, under control of said first processor, said microprogram in said second memory of said first module, said microprogram having been transferred to said transmission controller of said first module through said first common transmission path of said first module, said first module being in an initial state following a power-on sequence, starting up, under control of said first processor, said second processor of said first module; and storing, under control of said first processor, said microprogram in said second memory of said second module, said microprogram having been transferred from said first memory of said first module to said transmission controller of said second module through said first common transmission path of said module, said transmission controller of said first module and said second transmission path, said second module being in an initial state following a power-on sequence.
Claim 4
Independent Claim
320 words
A method for loading a microprogram in a second memory of a multiprocessor system including at least first and second modules each having, (a) a first processor for executing arithmetic processing and peripheral control, (b) a first memory for storing program and data wherein said program and data controls said first processor, (c) an input-output controller controlled by said controls external input-output devices, (d) a transmission controller controlled by said first processor wherein said transmission controller controls information transfers from/to another module, said transmission controller including a second processor for executing arithmetic processing and a second writable memory for storing microprogram wherein said microprogram controls said second processor, (e) a first common transmission path connected to said first processor, said first memory, said input-output controller and said transmission controller for permitting information transfers between said first processor, said first memory, said input-output controller and said transmission controller; and a second common transmission path respectively connected to transmission controllers of said modules for permitting information transfers between said first and second modules via said transmission controllers, said method comprising the steps of: storing, under control of said first processor, said microprogram in said second memory of said first module, said microprogram having been transferred to said transmission controller of said first module through said first common transmission path of said first module, said first module being in an initial state following a power-on sequence, starting up, under control of said first processor, said second processor of said first module; and storing, under control of said first processor, said microprogram in said second memory of said second module, said microprogram having been transferred from said first memory of said first module to said transmission controller of said second module through said first common transmission path of said module, said transmission controller of said first module and said second transmission path, said second module being in an initial state following a power-on sequence.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-11-27 | 1993-05-29 | 1993-11-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-11-27 | 1997-05-29 | 1997-11-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-11-27 | 2001-05-29 | 2001-11-28 | $7700.00 | Window Closed / Lapsed |