US4885719A
Expired / Lapsed
US
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Improved logic cell array using CMOS E2 PROM cells
Assignee: ANALOG TECHNOLOGY Inc
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Filing: 1987-08-19
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Granted: 1989-12-05
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Expires: 2007-08-19
Abstract
Abstract A programmable memory cell useful in a logic cell array draws no D.C. power in either a "1" or a "0" state. The cell includes a CMOS transistor pair including a p-channel transistor connected to a positive voltage source and an n-channel transistor connected to a circuit ground potential. The cell output is connected to a common terminal of the CMOS transistor pair. The CMOS transistor pair has a common floating gate which is selectively charged for programming the cell. In a preferred embodiment, the floating gate comprises a first polycrystalline silicon layer (polysilicon), and capacitive means including a second polysilicon layer spaced from and capacitively coupled with the first polysilicon layer is utilized to selectively applying charge to the common floating gate.
Inventors
- 👤 Dhaval J. Brahmbhatt
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 17:17
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/04; G11C16/0408; G11C16/0441; G11C16/045; H; H10; H10B; H10B69/00
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
148 words
A logic cell array comprising a plurality of configurable logic blocks arranged in rows and columns, each logic block including an electrically erasable programmable memory cell (E 2 PROM), said cell having a series connected CMOS transistor pair including a p-channel transistor having a source terminal connected to a positive voltage source and an n-channel transistor having a drain terminal connected a circuit ground potential, an output connected to a common terminal of said CMOS transistor pair, said CMOS transistor pair having a common floating gate, and means for selectively charging said common floating gate including capacitive means coupled to said floating gate, a programming electrode, a tunnelling oxide separating said programming electrode and said floating gate, and a programming transistor connected to said programming electrode for applying a programming voltage to said programming electrode for cold electron injection through said tunnelling oxide to said common floating gate.
Claim 2
Dependent Claim
148 words
A logic cell array comprising a plurality of configurable logic blocks arranged in rows and columns, each logic block including an electrically erasable programmable memory cell (E 2 PROM), said cell having a series connected CMOS transistor pair including a p-channel transistor having a source terminal connected to a positive voltage source and an n-channel transistor having a drain terminal connected a circuit ground potential, an output connected to a common terminal of said CMOS transistor pair, said CMOS transistor pair having a common floating gate, and means for selectively charging said common floating gate including capacitive means coupled to said floating gate, a programming electrode, a tunnelling oxide separating said programming electrode and said floating gate, and a programming transistor connected to said programming electrode for applying a programming voltage to said programming electrode for cold electron injection through said tunnelling oxide to said common floating gate.
Claim 3
Dependent Claim
41 words
The logic cell array as defined by claim 1 wherein said common floating gates comprises a first polycrystalline silicon layer and said capacitive means includes a second polycrystalline silicon layer spaced from, and capacitively coupled with, said first polycrystalline silicon layer.
Claim 4
Dependent Claim
127 words
An electrically erasable programmable memory cell (E 2 PROM) comprising a series connected CMOS transistor pair including a p-channel transistor having a source terminal connected to a positive voltage source and an n-channel transistor having a drain terminal connected to a circuit ground potential, an output connected to a common terminal of said CMOS transistor pair, said CMOS transistor pair having a common floating gate, and means for selectively charging said common floating gate including capacitive means coupled to said floating gate, a programming electrode, a tunnelling oxide separating said programming electrode and said floating gate, and a programming transistor connected to said programming electrode for applying a programming voltage to said programming electode for cold electron injection through said tunnelling oxide to said common floating gate.
Claim 5
Dependent Claim
127 words
An electrically erasable programmable memory cell (E 2 PROM) comprising a series connected CMOS transistor pair including a p-channel transistor having a source terminal connected to a positive voltage source and an n-channel transistor having a drain terminal connected to a circuit ground potential, an output connected to a common terminal of said CMOS transistor pair, said CMOS transistor pair having a common floating gate, and means for selectively charging said common floating gate including capacitive means coupled to said floating gate, a programming electrode, a tunnelling oxide separating said programming electrode and said floating gate, and a programming transistor connected to said programming electrode for applying a programming voltage to said programming electode for cold electron injection through said tunnelling oxide to said common floating gate.
Claim 6
Dependent Claim
45 words
The program memory cell as defined by claim 3 wherein said common floating gate comprises a first layer of polycrystalline silicon material and said capacitive means comprises a second layer of polycrystalline silicon material spaced from, and capacitively coupled with, said first polycrystalline silicon material.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-12-04 | 1993-06-05 | 1993-12-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-12-04 | 1997-06-05 | 1997-12-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-12-04 | 2001-06-05 | 2001-12-05 | $7700.00 | Window Closed / Lapsed |