Routing among field effect transistors

Claim 1

A method of routing terminals of field effect transistors in a cell having at least two field effect transistor rows each having a fixed transverse length, channels on said field effect transistor rows where single wiring layer can be used, a channel sandwiched between each pair of said field effect transistor rows, and having a fixed transverse length where double wiring layers can be used, and channels outside the field effect transistor rows where double wiring layers can be used, by using a feedthrough or feedthroughs traversing across the field effect transistor row for interconnecting the routings in these channels and by interconnecting diffusion layers and gates which are the terminals of the field effect transistors, comprising the steps of: dissolving given interconnections into two-terminal interconnections; selecting as many two-terminal interconnections from said dissolved two-terminal interconnections as possible provided that the respective selected two-terminal interconnections do not cause any shortcircuit; providing selection criteria of interconnection in routing on a wirable region of a channel on the field effect transistor row, selecting two-terminal interconnections to be routed in the channel on the field effect transistor row according to the criteria and routing the selected two-terminal interconnections; making a feedthrough for a non-selected two-terminal interconnection and routing the non-selected interconnection; and finally routing two-terminal interconnections in the channels where double wiring layers can be used.

Claim 2

A method of routing terminals of field effect transistors in a cell having at least two field effect transistor rows each having a fixed transverse length, channels on said field effect transistor rows where single wiring layer can be used, a channel sandwiched between each pair of said field effect transistor rows, and having a fixed transverse length where double wiring layers can be used, and channels outside the field effect transistor rows where double wiring layers can be used, by using a feedthrough or feedthroughs traversing across the field effect transistor row for interconnecting the routings in these channels and by interconnecting diffusion layers and gates which are the terminals of the field effect transistors, comprising the steps of: dissolving given interconnections into two-terminal interconnections; selecting as many two-terminal interconnections from said dissolved two-terminal interconnections as possible provided that the respective selected two-terminal interconnections do not cause any shortcircuit; providing selection criteria of interconnection in routing on a wirable region of a channel on the field effect transistor row, selecting two-terminal interconnections to be routed in the channel on the field effect transistor row according to the criteria and routing the selected two-terminal interconnections; making a feedthrough for a non-selected two-terminal interconnection and routing the non-selected interconnection; and finally routing two-terminal interconnections in the channels where double wiring layers can be used.