US4888731A
Expired / Lapsed
US
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Content addressable memory array system with multiplexed status and command information
Assignee: Advanced Micro Devices Inc
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Filing: 1988-05-11
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Granted: 1989-12-19
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Expires: 2008-05-11
Abstract
Abstract A content addressable memory system includes an array of memory cells arranged in rows and columns in an array of N bit cells by M words, with N bits per word, an I/O bus having a bit capacity S which is a submultiple of N, a mode generator for generating a plurality of commands, the commands including a command write command, a data write command, a data read command, and a status read command, the command write and the status read commands being encodable in S bits or less, and multiplexing means for supplying selected ones of the commands to the I/O bus.
Inventors
- 👤 Patrick T. Chuang
- 👤 Robert L. Yau
- 👤 Hiroshi Yoshida
- 👤 Moon-Yee Wang
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 23:37
CPC Classifications
G; G06; G06F; G06F16/00; G06F16/90; G06F16/903; G06F16/90335; G06F16/90339
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
188 words
A content addressable memory system comprising: an array of memory cells having an input and an output and arranged in rows and columns in an array of N bit cells by M words, with N bits per word; a comparand register having a capacity of N bits, said comparand register having an input and an output, means connecting said comparand register output to said input of said array of memory cells; an I/O bus carrying data, commands, and status information and having a bit capacity S which is a submultiple of N; means connecting said I/O bus to said input of said comparand register; means for supplying bits of said data from said I/O bus to said comparand register in cycles of no more than S bits per cycle; means for comparing said data supplied to said comparand register bit for bit with the contents of each of said M words in said array of memory cells; and means for indicating a match between said supplied data from said comparand register and the contents of one or more of said M words in said array of memory cells.
Claim 2
Dependent Claim
188 words
A content addressable memory system comprising: an array of memory cells having an input and an output and arranged in rows and columns in an array of N bit cells by M words, with N bits per word; a comparand register having a capacity of N bits, said comparand register having an input and an output, means connecting said comparand register output to said input of said array of memory cells; an I/O bus carrying data, commands, and status information and having a bit capacity S which is a submultiple of N; means connecting said I/O bus to said input of said comparand register; means for supplying bits of said data from said I/O bus to said comparand register in cycles of no more than S bits per cycle; means for comparing said data supplied to said comparand register bit for bit with the contents of each of said M words in said array of memory cells; and means for indicating a match between said supplied data from said comparand register and the contents of one or more of said M words in said array of memory cells.
Claim 3
Dependent Claim
67 words
A memory system in accordance with claim 1 in which each of said M words in said array of memory cells has a different address therein, said system including: means responsive to detection of a match between said compared data in said comparand register and said bits in one of said M words for indicating said address in said array of memory cells of said matching word.
Claim 4
Dependent Claim
77 words
A memory system in accordance with claim 1 in which each of said M words in said array of memory cells has a different address therein, said system including: means responsive to detection of a match between said compared data in said comparand register and said bits in more than one of said M words for indicating said address in said array of memory cells of the one of said matching words having the lowest order address.
Claim 5
Dependent Claim
30 words
A memory system in accordance with claim 3 including means for indicating a multiple match when more than one of said words matches said compared data from said comparand register.
Claim 6
Dependent Claim
89 words
A memory system in accordance with claim 1 including: a mask register having a capacity of N bits, said mask register having an input and an output; means for connecting said output of said comparand register to said input of said mask register; means for connecting said output of said mask register to said input of said comparand register; means, responsive to bits in said comparand register which are to be deleted from comparison by said comparing means, for masking said bits to be deleted through said mask register.
Claim 7
Dependent Claim
55 words
A memory system in accordance with claim 5 including: means for supplying said bits to be deleted from said comparison from said I/O bus through said comparand register to said mask register, and means for supplying said bits to be deleted from said mask register to said comparand register to delete the corresponding bits therein.
Claim 8
Dependent Claim
67 words
A memory system in accordance with claim 1 including: a mode generator for generating a plurality of commands, said commands including a command write command, a data write command, a data read command, and a status read command, said command write and said status read commands being encodable in S bits or less; and multiplexing means for supplying selected ones of said commands to said I/O bus.
Claim 9
Dependent Claim
43 words
A system in accordance with claim 7 including a status register; means for supplying said status read command to said status register; and means for supplying status information from said status register to said I/O bus in response to said status read command.
Claim 10
Dependent Claim
58 words
A system in accordance with claim 7 including an operation code generator connected to said I/O bus for generating one of a plurality of operation codes identifying different operations to be performed in said system; means for supplying said command write command to said operation code generator to cause said generator to generate one of said operation codes.
Claim 11
Dependent Claim
59 words
A system in accordance with claim 8 including means for detecting the fill condition of said array of memory cells; means for supplying an indication of said fill condition of said array to said status register; and means for supplying said fill condition indication from said status register to said I/O bus in response to said status read command.
References Cited (Backward Citations)
US4310901A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-12-18 | 1993-06-19 | 1993-12-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-12-18 | 1997-06-19 | 1997-12-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-12-18 | 2001-06-19 | 2001-12-19 | $7700.00 | Window Closed / Lapsed |