Dual modulus fractional divider

Claim 2

A dual modulus fractional divider having an effective modulus N, an input and an output, comprising: a prescaler coupled to said input, having a modulus P and a modulus (P+1); a programmable divider coupled to said prescaler; means for selectively programming said programmable divider with a modulus A, a modulus B, a modulus (A-1) and a modulus (B+1); and control means, including a rate multiplier, coupled to said prescaler, said programmable divider and said programming means for providing on said output of said fractional divider an output signal having a plurality of cycles with a frequency f out from an input signal applied to said input of said fractional divider having a plurality of cycles with a frequency f in wherein: ##EQU17## N=A×P+B×(P+1) N+1=(A-1)P+(B+1) (P+1) W=the radix of said rate multiplier, and Z=any number from 0 to (W-1) A=H-M-B B=L+P×H H=INT (N/P)=N(MOD P) M=INT {[N/P(2P+1)]-[L/P]+0.5 }, and L=N-P×H.

Claim 3

A dual modulus fractional divider having an input and an output comprising: a prescaler coupled to said input, having a modulus P and a modulus (P+1); a programmable divider coupled to said prescaler; means for selectively programming said programmable divider with a modulus A, a modulus B, a modulus (A-1) and a modulus (B+1); and control means, including a rate multiplier having an input for programming said multiplier with a fractional resolution integer Z, coupled to said prescaler, said programmable divider and said programming means for selectively providing and output signal on said output of said fractional divider having a plurality of cycles with a frequency f out equal to an input signal applied to said input of said fractional divider having a plurality of cycles with a frequency f in divided by (P) A times and by (P+1) B times when Z=0 and an output signal on said output of said fractional divider having a plurality of cycles with a frequency f out equal to an input signal applied to said input of said fractional divider having a plurality of cycles with a frequency f in divided by (N+1) C times and by N (W-C) times when Z=C and 0<C<W wherein: N=A×P+B×(P+1) N+1=(A-1)P+(B+1) (P+1) W=the radix of said rate multiplier, and Z=any number from 0 to (W-1) A=H-M-B B=L+P×H H=INT (N/P)=N(MOD P) M=INT{[N/P(2P+1)]-[L/P]+0.5}, and L=N-P×H.

Claim 4

A dual modulus fractional divider having an input and an output comprising: a prescaler coupled to said input, having a modulus P and a modulus (P+1); a programmable divider coupled to said prescaler; means for selectively programming said programmable divider with a modulus A, a modulus B, a modulus (A-1) and a modulus (B+1); and control means, including a rate multiplier having an input for programming said multiplier with a fractional resolution integer Z, coupled to said prescaler, said programmable divider and said programming means for selectively providing and output signal on said output of said fractional divider having a plurality of cycles with a frequency f out equal to an input signal applied to said input of said fractional divider having a plurality of cycles with a frequency f in divided by (P) A times and by (P+1) B times when Z=0 and an output signal on said output of said fractional divider having a plurality of cycles with a frequency f out equal to an input signal applied to said input of said fractional divider having a plurality of cycles with a frequency f in divided by (N+1) C times and by N (W-C) times when Z=C and 0<C<W wherein: N=A×P+B×(P+1) N+1=(A-1)P+(B+1) (P+1) W=the radix of said rate multiplier, and Z=any number from 0 to (W-1) A=H-M-B B=L+P×H H=INT (N/P)=N(MOD P) M=INT{[N/P(2P+1)]-[L/P]+0.5}, and L=N-P×H.

Claim 5

A dual modulus fractional divider having an input and an output, comprising: a prescaler coupled to said input, having a modulus P and a modulus (P+1); a programmable divider coupled to said prescaler having a plurality of moduluses including a modulus A, a modulus B, a modulus (A-1) and a modulus (B+1); first means responsive to an output from said programmable divider for changing said modulus of said prescaler between said modulus P and said modulus (P+1); and second means responsive to an output from said first means for selectively changing said modulus of said programmable divider between said modulus A, said modulus B, said modulus (A-1) and said modulus (B+1).

Claim 6

A dual modulus fractional divider having an input and an output, comprising: a prescaler coupled to said input, having a modulus P and a modulus (P+1); a programmable divider coupled to said prescaler having a plurality of moduluses including a modulus A, a modulus B, a modulus (A-1) and a modulus (B+1); first means responsive to an output from said programmable divider for changing said modulus of said prescaler between said modulus P and said modulus (P+1); and second means responsive to an output from said first means for selectively changing said modulus of said programmable divider between said modulus A, said modulus B, said modulus (A-1) and said modulus (B+1).

Claim 7

A dual modulus fractional divider according to claim 3 wherein said first means comprises a divide-by-2 circuit coupled between said programmable divider; and said prescaler, and said second means comprises: latching means; means for storing said modulus A and said modulus B in said latching means; means for adding and subtracting; means responsible to said divide-by-2 circuit for selectively transferring said modulus A and said modulus B from said latching means to said adding and subtracting means; a rate multiplier responsive to said divide-by-2 circuit for providing a first and a second output signal; means in said adding and subtracting means which is responsive to said first output signal from said rate multiplier for providing a first output signal from said adding and subtracting means which is equal to modulus A and to said second output signal from said rate multiplier for providing a second output signal from said adding and subtracting means which is equal to modulus (A-1) when said modulus A is being transferred to said adding and subtracting means, and responsive to said first output signal from said rate multiplier for providing a third output signal from said adding and subtracting means which is equal to modulus B and to said second output signal from said rate multiplier for providing a fourth output signal from said adding and subtracting means which is equal to modulus (B+1) when said modulus B is being transferred to said adding and subtracting means; and means for transferring said first, said second, said third and said fourth output signals from said adding and subtracting means to said programmable divider.

Claim 8

A dual modulus fractional divider according to claim 4 wherein said adding and subtracting means comprises a full adder, said modulus (A-1) is provided by adding the 1's complement to modulus A and said modulus (B+1) is provided by adding 1 to modulus B.

Claim 9

A dual modulus fractional divider according to claim 4 wherein said rate multiplier comprises a radix W and means for programming said rate multiplier with a value Z wherein Z is any number from 0 to (W-1).