US4894657A
Expired / Lapsed
US
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Pipelined analog-to-digital architecture with parallel-autozero analog signal processing
Assignee: General Electric Co
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Filing: 1988-11-25
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Granted: 1990-01-16
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Expires: 2008-11-25
Abstract
Abstract A pipelined analog-to-digital converter architecture comprises three pipeline stages wherein the first stage includes a low-resolution flash A/D subconverter (10), two sample-and-hold amplifiers (12 and 14), two D/A converters (16 and 18), and two unity-gain buffers (20 and 22). Parallel-autozero analog processing is accomplished by alternately passing the analog signal through one or the other of two parallel processing channels. The sampled analog signal is delivered to the flash A/D subconverter and the D/A converters simultaneously. The residue from the D/A converters is delivered to the second stage, passing through a flash A/D subconverter (24), an additional D/A converter (26), and alternately through two comparators (28 and 30) each having a gain of eight. The second stage produces and delivers its residual voltage to the final pipeline stage comprising a flash A/D subconverter (32). The unity-gain buffers require a minimal gain-bandwidth product for a given sampling rate and allow the architecture to operate at high speed, while the first stage D/A converters provide good accuracy.
Inventors
- 👤 Jyh-Ping Hwang
- 👤 Miran Milkovic
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 04:14
CPC Classifications
H; H03; H03M; H03M1/00; H03M1/10; H03M1/1004; H03M1/1009; H03M1/1014; H03M1/1023; H03M1/12; H03M1/14; H03M1/16; H03M1/164; H03M1/167
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
231 words
A pipelined analog-to-digital converter with parallel-autozero analog signal processing comprising: first and second sample-and-hold circuits for alternately sampling and holding an analog voltage signal to be converted to a digital code; a plurality of stages coupled in series in a pipeline, a first stage of the pipeline being connected to receive output signals from said first and second sample-and-hold circuits and producing a first part of said digital code and a residue voltage, each stage of the pipeline comprising a flash analog-to-digital subconverter, respectively, the subconverter of each of an intermediate and a final stage converting a residue voltage from a preceding stage to a succeeding part of said digital code, each of the first and intermediate stages including parallel circuit paths; first switching means coupled to said first and second sample-and-hold circuits and to said parallel circuit path in said first stage for alternately connecting one of said first and second sample-and-hold circuits, respectively, and said parallel circuit path of said first stage in a signal path and for autozeroing the sample-and-hold circuit and circuit path not connected in said signal path; and second switching means coupled to said parallel circuit path in said second stage for alternately connecting said parallel circuit path of said second stage in said signal path; whereby signal flow at the output of said pipelined analog-to-digital converter is continuous without degradation due to offset voltages.
Claim 2
Dependent Claim
231 words
A pipelined analog-to-digital converter with parallel-autozero analog signal processing comprising: first and second sample-and-hold circuits for alternately sampling and holding an analog voltage signal to be converted to a digital code; a plurality of stages coupled in series in a pipeline, a first stage of the pipeline being connected to receive output signals from said first and second sample-and-hold circuits and producing a first part of said digital code and a residue voltage, each stage of the pipeline comprising a flash analog-to-digital subconverter, respectively, the subconverter of each of an intermediate and a final stage converting a residue voltage from a preceding stage to a succeeding part of said digital code, each of the first and intermediate stages including parallel circuit paths; first switching means coupled to said first and second sample-and-hold circuits and to said parallel circuit path in said first stage for alternately connecting one of said first and second sample-and-hold circuits, respectively, and said parallel circuit path of said first stage in a signal path and for autozeroing the sample-and-hold circuit and circuit path not connected in said signal path; and second switching means coupled to said parallel circuit path in said second stage for alternately connecting said parallel circuit path of said second stage in said signal path; whereby signal flow at the output of said pipelined analog-to-digital converter is continuous without degradation due to offset voltages.
Claim 3
Dependent Claim
54 words
The pipelined analog-to-digital converter of claim 1 wherein said first stage additionally comprises a unity-gain amplifier in each of said parallel circuit paths, respectively, supplying a residual voltage from said first stage to a second stage so as to require a minimal gain band-width product and allow the converter to operate at high speed.
Claim 4
Dependent Claim
117 words
The pipelined analog-to-digital converter of claim 2 wherein said first stage additionally comprises a pair of digital-to-analog converters, the sampled and held voltages of said first and second sample-and-hold circuits being delivered to said flash analog-to-digital subconverter of said first stage and to each of said digital-to-analog converters simultaneously, said first part of said digital code being supplied by the flash analog-to-digital subconverter of said first stage to each of said digital-to-analog converters, the outputs of said digital-to-analog converters being alternately coupled by a respective one of said unity-gain amplifiers to the flash analog-to-digital subconverter of the second stage of the pipeline so as to supply thereto, in alternating fashion, the residual voltage of the first stage.
Claim 5
Dependent Claim
85 words
The pipelined analog-to-digital converter of claim 3 wherein the intermediate stage of the pipeline additionally comprises digital-to-analog converter means and a pair of amplifiers having identical gains greater than one coupled to the flash analog-to-digital subconverter of the final stage, a second part of said digital code produced by the flash analog-to-digital subconverter of said intermediate stage being supplied to said digital-to-analog converter means, and means coupling an output of said digital-to-analog converter means alternately to one or the other of said pair of amplifiers.
Claim 6
Dependent Claim
16 words
The pipelined analog-to-digital converter of claim 1 wherein said preceding stage comprises an immediately preceding stage.
Claim 7
Dependent Claim
18 words
The pipelined analog-to-digital converter of claim 3 wherein each of said digital-to-analog converters comprises a capacitive digital-to-analog converter.
Claim 8
Dependent Claim
36 words
The pipelined analog-to-digital converter of claim 4 wherein said flash analog-to-digital subconverter means produces an output code of n 2 bits and the gain of each one of said pair of amplifiers is 2.spsp.n 2 .spsp.-1.
Claim 9
Dependent Claim
17 words
The pipelined analog-to-digital converter of claim 4 wherein said digital-to-analog converter means comprises a resistive digital-to-analog converter.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-01-15 | 1993-07-17 | 1994-01-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-01-15 | 1997-07-17 | 1998-01-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-01-15 | 2001-07-17 | 2002-01-16 | $7700.00 | Window Closed / Lapsed |