US4894692A
Expired / Lapsed
US
⏱️ 0.0 years remaining
MESFET with alpha particle protection
Assignee: Mitsubishi Electric Corp
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Filing: 1988-06-02
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Granted: 1990-01-16
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Expires: 2008-06-02
Abstract
Abstract An integrated circuit includes a semi-insulating semiconductor substrate; a first conductivity type high dopant concentration buried layer produced in the semi-insulating substrate; second conductivity type high dopant concentration drain and source regions produced at the surface of the semi-insulating substrate; a gate electrode produced on the surface of the semi-insulating substrate at a position between the drain and source regions; a second conductivity type channel layer produced between the drain and source regions; and a first conductivity type low dopant concentration region produced only below the second conductivity type channel layer between the second conductivity type drain and source regions in the first conductivity type high dopant concentration region; the drain and source regions being completely surrounded by the first conductivity type high dopant concentration buried layer from the bottom and outer side surfaces thereof. Alternatively, a first conductivity type high dopant concentration buried layer is provided only below and at outer side surfaces of the drain layer and a first conductivity type low dopant concentration buried layer is provided below the channel layer and the source region and at the outer side surface of the source region.
Inventors
- 👤 Minoru Noda
- 👤 Noriyuki Tanino
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 22:19
CPC Classifications
H; H10; H10D; H10D62/00; H10D62/10; H10D62/17; H10D62/351; H10D62/357; H10D62/213; H10D62/221; H10D84/00; H10D84/01; H10D84/02; H10D84/05; H10D86/00; H10D86/01; Y; Y10; Y10S; Y10S257/00; Y10S257/906
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
151 words
An integrated circuit comprising: a semi-insulating semiconductor substrate having a surface; a first conductivity type embedded region disposed in said semi-insulating substrate; second conductivity type drain and source regions disposed in and at the surface of said semi-insulating substrate; a gate electrode disposed on the surface of said semi-insulating substrate between said drain and source regions; a second conductivity type channel layer disposed in said substrate and at the surface proximate said gate electrode between said drain and source regions; and a first conductivity type buried region disposed in said substrate between and bounded by said channel layer, said drain and source regions, and said embedded region, said drain and source regions being completely surrounded in said substrate by and contiguous with said embedded region wherein said embedded region is heavily doped relative to said buried region and said source and drain regions are heavily doped relative to said channel layer.
Claim 2
Dependent Claim
151 words
An integrated circuit comprising: a semi-insulating semiconductor substrate having a surface; a first conductivity type embedded region disposed in said semi-insulating substrate; second conductivity type drain and source regions disposed in and at the surface of said semi-insulating substrate; a gate electrode disposed on the surface of said semi-insulating substrate between said drain and source regions; a second conductivity type channel layer disposed in said substrate and at the surface proximate said gate electrode between said drain and source regions; and a first conductivity type buried region disposed in said substrate between and bounded by said channel layer, said drain and source regions, and said embedded region, said drain and source regions being completely surrounded in said substrate by and contiguous with said embedded region wherein said embedded region is heavily doped relative to said buried region and said source and drain regions are heavily doped relative to said channel layer.
Claim 3
Dependent Claim
15 words
An integrated circuit as defined in claim 1 wherein said semi-insulating semiconductor substrate comprises GaAs.
Claim 4
Dependent Claim
15 words
An integrated circuit as defined in claim 2 wherein said semi-insulating semiconductor substrate comprises InP.
Claim 5
Dependent Claim
139 words
An integrated circuit device comprising: a semi-insulating semiconductor substrate having a surface; second conductivity type drain and source regions disposed in said substrate at the surface of said semi-insulating substrate; a gate electrode disposed on the surface of said semi-insulating substrate between said drain and source regions; a second conductivity type channel layer disposed in said substrate at the surface proximate said gate electrode between said drain and source regions; a first conductivity type embedded layer surrounding said drain region in said substrate except proximate said channel layer; and a first conductivity type first buried layer disposed in said substrate surrounding said channel layer and said source region except proximate said drain region wherein said embedded layer is heavily doped relative to said buried layer and said source and drain regions are heavily doped relative to said channel layer.
Claim 6
Dependent Claim
139 words
An integrated circuit device comprising: a semi-insulating semiconductor substrate having a surface; second conductivity type drain and source regions disposed in said substrate at the surface of said semi-insulating substrate; a gate electrode disposed on the surface of said semi-insulating substrate between said drain and source regions; a second conductivity type channel layer disposed in said substrate at the surface proximate said gate electrode between said drain and source regions; a first conductivity type embedded layer surrounding said drain region in said substrate except proximate said channel layer; and a first conductivity type first buried layer disposed in said substrate surrounding said channel layer and said source region except proximate said drain region wherein said embedded layer is heavily doped relative to said buried layer and said source and drain regions are heavily doped relative to said channel layer.
Claim 7
Dependent Claim
15 words
An integrated circuit as defined in claim 4 wherein said semi-insulating semiconductor substrate comprises GaAs.
Claim 8
Dependent Claim
15 words
An integrated circuit as defined in claim 4 wherein said semi-insulating semiconductor substrate comprises InP.
Claim 9
Dependent Claim
25 words
An integrated circuit as defined in claim 4 including a second first conductivity type buried layer disposed in said substrate surrounding said first buried layer.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-01-15 | 1993-07-17 | 1994-01-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-01-15 | 1997-07-17 | 1998-01-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-01-15 | 2001-07-17 | 2002-01-16 | $7700.00 | Window Closed / Lapsed |